JTAG

Teach new tricks to your FPGA!

JTAG project

This project has 4 parts:

• Part 1: What is JTAG?
• Part 2: How JTAG works
• Part 3: Query the JTAG chain
• Part 4: Run a boundary-scan

JTAG tutorial source code

The tutorial source code can be used with Xilinx parallel-III and Altera ByteBlasterMV/II cables.
It is written in C. Get it here.

Material used to write/tested with this project's code:

• Pluto-P board (used in Xilinx/Altera JTAG cable emulation mode). Also tested on XP3/AB2 cable.
• Dragon Xilinx Spartan-2 board (IDCODE: 80610093 = Manuf 49, Part size 10, Family code 3, Rev 8).
• Saxo Altera Cyclone board (IDCODE: 020810DD = Manuf 6E, Part size 81, Family code 10, Rev 0).

Links

• An Introduction to JTAG Boundary Scan from Sun Microelectronics.
• A JTAG Boundary Scan presentation from TI (PDF).
• A Boundary Scan Tutorial from ASSET InterTech, Inc. (PDF).
• Boundary-Scan Testing in Altera Devices.
• The SVF Format for Xilinx Devices.
• The AP-630 from Intel.
• The SVF specification from ASSET and TI.

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This page was last updated on February 13 2008.