 |
|
An FPGA can be into 2 states: "configuration mode" or "user mode". When the FPGA wakes up after power-up, it is in configuration mode, sitting idle with all its outputs inactive. You need to configure it.
Configuring an FPGA means downloading a stream of 0's and 1's into it through some special pins. Once the FPGA is configured, it goes into "user-mode" and becomes active, performing accordingly to your programmed "logic function".
There are 3 classical ways to configure your FPGA:
During development, the first method is the easiest and quickest. Once your FPGA design works, you probably don't need the PC anymore, so the other 2 methods come in use.
Configuration works in a surprisingly identical way between Xilinx and Altera devices. The differences is mostly in the naming (pin names and modes of operation are named differently), but the functionality provided is similar.
Most FPGAs can be be configured in multiple ways, using either:
FPGA configuration can quickly become a complex subject, so you might want to skip this section, especially if you intend to use an already-made FPGA development board.
Development boards usually come with a special cable that you can use to configure the FPGA from your PC with no knowledge of the underlying interface.
But if you want to learn a little more, read-on.
JTAG was originally designed for test and manufacturing purposes (as electronic boards became more and more compact, testing that a board was "good" became more and more difficult).
JTAG primary purpose is to allow a computer to take control of the state of all the device pins on a board. In turn, this allows all device-to-device combinations on the board to be tested. Standard JTAG commands can be used for this purpose.
FPGAs are JTAG-aware and so all the FPGA IO pins can be controlled from the JTAG interface. FPGAs add the ability to be configured through JTAG (using proprietary JTAG commands).
JTAG consists of 4 signals: TDI, TDO, TMS and TCK.
A fifth pin, TRST, is optional.
A single JTAG port can connect to one or multiple devices (as long as they are all JTAG-aware parts). With multiple devices, you create what is called a "JTAG chain". The TMS and TCK are tied to all the devices directly, but the TDI and TDO form a chain: TDO from one device goes to TDI of the next one in the chain. The master controlling the chain (a computer usually) closes the chain.
TCK is the clock, TMS is used to send commands to the devices, and TDI/TDO are used to send and receive data. Each device in the chain has an ID, so the computer controlling the JTAG chain can figure out which devices are present.
For more info, check the JTAG project.
It is a simple data/clock interface. It is synchronous and you provide one bit at a time to the FPGA.
Here's a description of the 5 most important pins of this interface:
| Xilinx pin name | Altera pin name | Direction | Pin function |
| data | data0 | input to the FPGA | configuration data bit |
| clk | dclk | input to the FPGA | configuration clock, the configuration data bit is shifted in the FPGA at the clock rising-edge |
| prog_b | nConfig | input to the FPGA | When asserted (i.e. when it goes low - this is an active low pin), the FPGA is reset-ed and looses its configuration. If the FPGA was in user-mode, it stops operation immediately, and all IOs go back into tri-state mode. |
| init_b | nStatus | output from the FPGA | This pin indicates when the FPGA is ready to start the configuration process, soon after prog_b is de-asserted. It is useful in combination with prob_b because it takes a few milliseconds for the FPGA is get into a "clean state of mind", once prog_b is de-asserted, after which pumping configuration data can actually start. |
| done | ConfDone | output from the FPGA | When high, indicates that the FPGA is configured (in user-mode). |
Note: the init_b and done pins are actually open-collector pins, so pull-up resistors are required on these. Also if multiple FPGAs are to be configured, these pins are usually connected together on all FPGAs, so that all the FPGAs switch into "user-mode" together. There is many more details, so for a complete description, check your FPGA datasheet.