Crossing clock domains

An FPGA design can use multiple clocks. Each clock forms a "clock domain" inside the FPGA, and care needs to be taken if a signal generated in a clock domain is needed in another clock domain.

Crossing in four parts

• Part 1: Signal crossing
• Part 2: Flag crossing
• Part 3: Task crossing
• Part 4: Data bus crossing

BTW, to learn about metastablity (or why so much hard work is needed to cross clock domains), check the links below.

Links

• What is Metastability? and Interfacing Two Clock Domains from World of ASIC.
• Metastability in electronics from Wikipedia.
• Synchronization in Digital Logic Circuits from Ryan Donohue (PDF presentation).
• Clock domain crossing from Cadence (PDF).
• Understanding Clock Domain Crossing Issues from EDA DesignLine.
• Clock domain crossing using SystemVerilog from Sunburst Design, Inc. (PDF).

>>> NEXT - part 1: Crossing clock domains - Signal >>>

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This page was last updated on May 19 2013.