Crossing clock domains
An FPGA design can use multiple clocks.
Each clock forms a "clock domain" inside the FPGA, and care needs to be taken if a signal generated in a clock domain is needed in another clock domain.
Crossing in four parts
BTW, to learn about metastablity (or why so much hard work is needed to cross clock domains), check the links below.
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This page was last updated on May 18 2013.