There are 2 methods:
With schematic design entry, you draw your design on your computer using gates and wires.
Schematic entry is nice because it documents the design in an easily readable format. But big designs quickly become difficult to maintain, the file formats are incompatibles between vendors, and HDLs are easier to parameterize, so many FPGA users quickly shy away from schematic design entry.
Vendors used to have proprietary languages. But then came two HDL languages (VHDL and Verilog) that quickly got popular. Now FPGA vendors support mainly these two languages.
Learning an HDL takes an effort, and this is probably the most important thing you'll have to learn when diving into the FPGA world. This website makes it somehow easier since you can learn from examples. And your time-investment is protected because these languages are now industry standards.
Ok, let's implement a set of AND and OR gates, like that:
The HDL code looks like that:
module gates(a, b, q, r);
input a, b;
output q, r;
assign q = a & b;
assign r = a | b;
entity gates is
port( a,b: in std_logic;
q,r: out std_logic);
architecture implement of gates is
q <= a and b;
r <= a or b;
Now let's look on how to create a D flip-flop:
module d_flipflop(clk, d, q);
input clk, d;
always @(posedge clk) q <= d;
entity d_flipflop is
port( clk, d: in std_logic;
q: out std_logic);
architecture implement of d_flipflop is
if clk'EVENT and clk='1' then
q <= d;
With both languages, notice how the D flip-flop is expressed by its behavior (i.e. at each positive clock edge, copy the 'd' input to the 'q' output). VHDL and Verilog are called "behavioral languages" because of that.
These two examples are synthesizable (you can directly put them into an FPGA), but behavioral languages can also produce...
Using a behavioral language, you can describe a circuit that has no hardware equivalent. For example a flip-flop that takes 2 clocks can be simulated but not synthesized.
module d_flipflop_2clks(clk1, clk2, d, q);|
input clk1, clk2, d;
always @(posedge clk1 or posedge clk2) q <= d;
Which language to use is a matter of preference, they have similar characteristics. Verilog is simpler to learn and use (in our opinion), so that's what we use in this website.