FPGA pin assignment

Your FPGA needs to communicate with the outside world. The signals that are exported from your design are connected to the FPGA user pins (if your design is hierarchical, the signals from your "top-level" are the only ones connected to the user pins).

The top-level file usually does not specify which signal goes to which pin. If you do not specify anything, the FPGA software chooses the pins randomly. For most practical purpose, you need to create a "pin assignment" that will specify with signal goes to which pin.

A pin assignment file does not specify the direction of the signals (input or an output), only the "signal name <--> pin" relation.
Pin assignment files are text files, but with a proprietary format.

Xilinx pin assignment files

Xilinx uses a ".ucf" file.
The pin assignment section looks like that:

NET "data" LOC = "P17"; NET "clock" LOC = "P91"; ...

So for example, the signal "data" will go in pin 17.
The UCF file can also contain timing constraints (not shown above).

Altera pin assignment files

Altera's Quartus uses a ".qsf" file (or a ".csf" file in older versions of Quartus).
The file contains the pin assignment, but also other information.

The .qsf pin assignment part looks like:

set_location_assignment PIN_10 -to clk set_location_assignment PIN_26 -to LED ...

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This page was last updated on April 02 2007.