The FPGA software major task, in addition to facilitate design-entry, is to synthesize and place-and-route your design. What does this mean?
Synthesis takes your design (HDL or schematic) and creates a flat netlist out of it.
A netlist is just that, a "list of nets", connecting basic gates or flipflops together. The format of the netlist file can be proprietary, but the "EDIF" format is now the industry standard. Flat means the netlist doesn't have a hierarchy; it's one big file with all the nets in it (but the net names might still reflect the hierarchy of your original design).
Synthesis can be done by the FPGA vendor's (free or non-free) software, but can also be done by third-party (non-free) software, and since both the HDL languages and EDIF formats are now industry standards, many companies have taken the challenge and provide such software. Doing the synthesis using third-party software usually yields better-optimized netlists, which means you can put more and/or faster logic into your FPGAs.
Place-and-route (P&R) describes several processes where the netlist elements are physically places and mapped to the FPGA physical resources, to create a file that can be downloaded in the FPGA chip.
P&R can take a few seconds for a small FPGA, or a few hours for a big one.
P&R is always done by the FPGA software from the FPGA vendor, because FPGA vendors do not publish enough information about the internals of their devices to allow any other company to create P&R software. I guess other companies could try to reverse-engineer the information, but for now, you'll have no choice but to use the FPGA vendor software for P&R.
After synthesis and P&R, you have a binary file that is ready to be "downloaded" into the FPGA.