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How do you describe the hardware that you want to implement into an FPGA?
There are 2 methods:
With schematic design entry, you draw your design on your computer like you would draw it on paper, using gates and wires.
Schematic entry is nice because it documents the design in an easily readable format. But big designs quickly become difficult to maintain, the file formats are incompatibles between vendors, and HDL are easier to parameterize, so many FPGA users shy away from schematic design entry.
Each vendor used to have its own proprietary languages. But some 10 years ago came 2 new languages ("Verilog" and "VHDL") high-level HDLs (hardware description languages), that quickly got popular for chip and FPGA design. FPGA vendors started supporting mainly these 2 languages.
High-level HDLs are nowadays the preferred way to create FPGA designs. They also make migrations much easier.
Learning an HDL takes an effort, and this is probably the most important thing you'll have to learn when diving into the FPGA world. This website makes things somehow easier since you can learn from the example designs. And by learning an high-level HDL, your time-investment is protected because these languages are now industry standards.
Ok, let's implement a set of AND and OR gates, like that:
The HDL code looks like that:
| Verilog | VHDL |
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module gates(a, b, q, r); input a, b; output q, r; assign q = a & b; assign r = a | b; endmodule |
library ieee; use ieee.std_logic_1164.all; entity gates is port( a,b: in std_logic; q,r: out std_logic); end; architecture implement of gates is begin q <= a and b; r <= a or b; end; |
As you can see, Verilog is pretty straightforward, while VHDL requires additional declarations.
Now let's look on how to create a D-flipflop:
| Verilog | VHDL |
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module d_flipflop(clk, d, q); input clk, d; output q; reg q; always @(posedge clk) begin q <= d; end endmodule |
library ieee; use ieee.std_logic_1164.all; entity d_flipflop is port( clk, d: in std_logic; q: out std_logic); end; architecture implement of d_flipflop is begin process(clk) begin if clk'EVENT and clk='1' then q <= d; end if; end process; end; |
Here things are more complicated. To get a D-flipflop, you have to describe its behavior by saying "at each positive clock edge, please copy the 'd' input to the 'q' output". This is why these languages are called "behavioral languages". This example is synthesizable (you can directly put it into an FPGA), but behavioral languages can also produce non-synthesizable designs.
Using a behavioral language, you can describe a circuit that has no hardware equivalent.
This type of circuit can only be run in an HDL simulator.
For example:
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module d_flipflop_2clks(clk1, clk2, d, q); input clk1, clk2, d; output q; reg q; always @(posedge clk1 or posedge clk2) begin q <= d; end endmodule |
This circuit describes a flipflop that takes 2 clocks.
Such circuit has no direct hardware equivalent (no synthesis software will be able to process it).
But HDL simulators are just happy with it.