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FPGA projects - Basic
Music box
LED displays
Pong game
R/C servos
Text LCD module
Quadrature decoder
PWM and one-bit DAC
Debouncer
Crossing clock domains
The art of counting
External contributions

Interfaces
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Advanced
Digital oscilloscope
Graphic LCD panel
Direct Digital Synthesis
CNC steppers
Spoc CPU core

Hands-on
A simple oscilloscope


FPGA introduction
What are FPGAs?
How FPGAs work
Internal RAM
FPGA pins
Clocks and global lines
Download cables
Configuration
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FPGA software
Design software
Design-entry
Simulation
Pin assignment
Synthesis and P&R

FPGA electronic
SMD technology
Crystals and oscillators

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ISE
Quartus-II

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FPGA pin assignment

Your FPGA needs to communicate with the outside world. The signals that are exported from your design are connected to the FPGA user pins (if your design is hierarchical, the signals from your "top-level" are the ones connected to the user pins).

The top-level file usually does not specify which signal goes to which pin. If you do not specify anything, the FPGA software makes a (more or less) random assignment. For most practical purpose, you need to create pin assignments.

Pin assignment files are text files, but with a proprietary format.

Xilinx pin assignment file

ISE uses ".ucf" files. They look like that:

NET "clk" LOC = "P91";
NET "LED" LOC = "P17";
...

The UCF file can also contain timing constraints (not shown above).

Altera pin assignment file

Quartus-II uses ".qsf" files (".csf" files in older versions of Quartus) that are created automatically by Quartus-II (they contain the pin assignments, but also all the project settings).

The .qsf pin assignment part looks like this:

set_location_assignment PIN_10 -to clk
set_location_assignment PIN_26 -to LED
...


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This page was last updated on May 21 2013.