Your FPGA needs to communicate with the outside world. The signals that are exported from your design are connected to the FPGA user pins (if your design is hierarchical, the signals from your "top-level" are the ones connected to the user pins).
The top-level file usually does not specify which signal goes to which pin. If you do not specify anything, the FPGA software makes a (more or less) random assignment. For most practical purpose, you need to create pin assignments.
Pin assignment files are text files, but with a proprietary format.
ISE uses ".ucf" files. They look like that:
NET "clk" LOC = "P91";|
NET "LED" LOC = "P17";
The UCF file can also contain timing constraints (not shown above).
Quartus-II uses ".qsf" files (".csf" files in older versions of Quartus) that are created automatically by Quartus-II (they contain the pin assignments, but also all the project settings).
The .qsf pin assignment part looks like this:
set_location_assignment PIN_10 -to clk|
set_location_assignment PIN_26 -to LED