FPGA simulation

Once the hardware design entry is completed (either using a schematic or HDL), you may want to simulate your design on a computer to gain confidence that it works correctly.

Simulation requires a form of stimulus to provide to the inputs of the FPGA design, and then an FPGA simulator software can determine the corresponding FPGA outputs.

There are 2 ways you can create the simulation stimulus:

• Using an interactive waveform editor.
• Using a testbench.

Interactive waveform editor

Using an interactive waveform editor, you enter the shape of the inputs (with a few clicks of your computer mouse), and the simulator software draws the shape of the outputs.

If you are just starting to play with FPGAs, try an interactive waveform editor first since it is easier than writing testbenches.

Testbench designs

A testbench design is a non-synthesizable HDL file that creates stimulus for another (usually synthesizable) file.
Here's an example:

Let's assume that this synthesizable circuit needs to be exercised.

module gates(a, b, q, r); input a, b; output q, r; assign q = a & b;    // one AND gate assign r = a | b;     // one OR gate endmodule

A testbench could be:

module testbench_for_gates; // we create some stimulus by toggling the signals "a" and "b" every 50 time-units reg a, b; initial begin   a = 0; b = 0;   #50 a = 1;   #50 a = 0; b = 1;   #50 a = 1;   #50 $finish; end // and we apply the stimulus to "gates". In response, "gates" drives "q" and "r" signals wire q, r; gates my_gates(a, b, q, r); // and we can verify that "q" and "r" have the right values always @(a or b) if(q != (a & b)) $display("ERROR in signal q"); always @(a or b) if(r != (a | b)) $display("ERROR in signal r"); endmodule

The testbench is usually written in the same behavioral language (VHDL or Verilog) than your circuit under test.
VHDL and Verilog have different strengths. For example, advanced users might like VHDL's advanced type structures, or Verilog's interface with C code (Verilog "PLI").

HDL simulator

A testbench is run (simulated) using an "HDL simulator". FPGA software don't include HDL simulators. Sometimes you can get a free time-limited trial of a commercially available simulator with FPGA software. Or try one of these:

• The free Icarus Verilog simulator (PC Linux and Windows)
• Pragmatic's free Cver GPL Verilog simulator (PC Linux, Sparc Solaris and Apple Mac OS X)
• The FreeHDL GPL VHDL simulator (PC Linux)
• The VHDL Simili VHDL simulator (free for personal use)
• The GHDL VHDL simulator
• A list of free and commercial Verilog tools

VCD simulation viewer

The HDL simulator can, while running the simulation, record every signal and write them to a "VCD" file. That allows in turn to use a graphical VCD viewer to look at the signal values during the simulation. Try the free GTKWave waveform viewer.

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This page was last updated on April 02 2007.