Home
Welcome
Information


FPGA projects
Basic
Music box
LED displays
Pong game
R/C servos
Text LCD module
Quadrature decoder
PWM and one-bit DAC
Debouncer
Crossing clock domains
External contributions

Interfaces
RS-232
JTAG
I2C
EPP
SPI
PCI
PCI Express
10BASE-T

Advanced
Digital oscilloscope
Graphic LCD panel
Direct Digital Synthesis
CNC steppers
Spoc CPU core

Hands-on
A simple oscilloscope


FPGA introduction
What are FPGAs?
How FPGAs work
Internal RAM
FPGA pins
Clocks and global lines
Download cables
Configuration
Learn more

FPGA software
Design software
Pin assignment
Design-entry/HDL
Simulation/HDL
Synthesis and P&R

FPGA electronic
SMD technology
Crystals and oscillators

HDL info
HDL tutorials
Verilog tips
VHDL tips

Quick-start guides
ISE
Quartus

Site
News
FPGA links
HDL tutorials
Forum


Graphic LCD panel - video generator

Prior to be able to display anything on the panel, we need to generate video-sync signals (H-sync and V-sync).

The LCD used for this project has the following characteristics:

With a 4-bits data input, we need 480/4=120 clocks horizontally.
With 320 lines, a complete video frame takes 120x320=38400 clocks.

The code looks like that:

parameter ScreenWidth = 480;
parameter ScreenHeight = 320;

reg [6:0] CounterX;  // counts from 0 to 119
reg [8:0] CounterY;  // counts from 0 to 319
wire CounterXmaxed = (CounterX==ScreenWidth/4-1);
wire CounterYmaxed = (CounterY==ScreenHeight-1);

always @(posedge clk)
begin
  if(CounterXmaxed)
    CounterX <= 0;
  else
    CounterX <= CounterX + 1;
end

always @(posedge clk)
if(CounterXmaxed)
begin
  if(CounterYmaxed)
    CounterY <= 0;
  else
    CounterY <= CounterY + 1;
end

reg HSync, VSync;
always @(posedge clk)
begin
  HSync <= CounterXmaxed;
  VSync <= CounterYmaxed;
end

Now, let's provide data to be displayed - first some graphics, then some text.



>>> NEXT: Graphic LCD panel - Graphics >>>



This page was last updated on January 03 2008.