| fpga4fun.com - where FPGAs are fun. |
Here's the FPGA motion controller block diagram (three axes shown):
The USB-2 data gets buffered in a FIFO and then goes to a demultiplexor. Since the data is "packetized", the demultiplexor is necessary to distribute the acceleration data to each integrator's axis. After the integrators, pulse generators make sure the Step/Dir pulses have the proper timing.
Here's the integrator's heart.
The complete Verilog code weights about 200 lines and is available from KNJN.com.