HDL languages are nowadays the preferred way to create FPGA designs. The most commonly used HDL languages are Verilog and VHDL. This site showns examples in Verilog, but VHDL could have been used, as they are equivalent for most purposes.
For an in-depth discussion, take a look to VHDL & Verilog Compared & Contrasted (PDF).
Here are a few tutorials:
Finally Testbench.in with Verilog, Systemverilog, OpenVera, VMM, RVM, AVM, OVM tutorials.