An FPGA design can use multiple clocks. Each clock forms a "clock domain" inside the FPGA, and care needs to be taken if a signal generated in a clock domain is needed in another clock domain.

Crossing in four parts

1. Signal crossing
2. Flag crossing
3. Task crossing
4. Data bus crossing

BTW, to learn about metastability (or why so much hard work is needed to cross clock domains), check the links below.

Links

• What is Metastability? and Interfacing Two Clock Domains from World of ASIC.
• Metastability in electronics from Wikipedia.
• Synchronization in Digital Logic Circuits from Ryan Donohue (PDF presentation).
• Clock domain crossing from Cadence (PDF).
• Understanding Clock Domain Crossing Issues from EDA DesignLine.
• Clock domain crossing using SystemVerilog from Sunburst Design, Inc. (PDF).

• Crossing clock domains 1 - Signal ❯