Crossing clock domains
An FPGA design can use multiple clocks.
Each clock forms a "clock domain" inside the FPGA, and care needs to be taken if a signal generated in a clock domain is needed in another clock domain.
Crossing in four parts
- Signal crossing
- Flag crossing
- Task crossing
- Data bus crossing
BTW, to learn about metastability (or why so much hard work is needed to cross clock domains), check the links below.