Let's say a signal from clkA domain is needed in clkB domain. It needs to be "synchronized" to clkB domain, so we want to build a synchronizer design, which takes a signal from clkA domain, and creates a new signal into clkB domain.
In this first design, we assume that the "Signal-in" changes slowly compared to both clkA and clkB clock speeds.
All you need to do is to use two flip-flops to move the signal from clkA to clkB (to learn why, get back to the links).
The two flip-flops have the side-effect of delaying the signal.
For example, here are waveforms where you can see the slow moving signal being synchronized (and delayed) to clkB domain by the two flip-flops: