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FPGAs 7 - Configuration

An FPGA can be into 2 states: "configuration mode" or "user mode".
When an FPGA wakes up after power-up, it is in configuration mode, sitting idle with all its outputs inactive. You need to configure it.

Configuring an FPGA means downloading a stream of 0's and 1's through some special pins. Once the FPGA is configured, it goes into "user-mode" and becomes active.

There are three classical ways to configure your FPGA:

During development, the first method is the easiest and quickest. Once your FPGA design works, you probably don't need the PC anymore, so the other two methods come into use.

Configuration works in surprisingly identical ways between Xilinx and Altera devices. The differences are mostly in the naming (pin names and modes of operation are named differently), but the functionality is similar.

Most FPGAs have two sets of pins dedicated to configuration:

FPGA configuration can quickly become a complex subject, so you might want to skip this section, especially if you intend to use an already-made FPGA development board. Development boards usually come with a JTAG cable, or a special cable that you can use with no knowledge of the underlying interface. But if you want to learn a little more, read-on.

The JTAG interface (or JTAG "port")

FPGAs have the ability to be configured through JTAG (using proprietary JTAG commands). Note that JTAG was originally designed for test and manufacturing purposes (to allow a computer to take control of the device pins). FPGAs are certainly JTAG-testing able too.

See here for more info.

The "synchronous serial" interface

It is a simple data/clock interface. It is synchronous and you usually provide one bit at a time to the FPGA.

Here's a description of the five most important pins of this interface:

Xilinx pin name Altera pin name Direction Pin function
data data0 FPGA input configuration data bit
clk dclk FPGA input configuration clock (the configuration data bit is shifted in the FPGA at the clock rising-edge)
prog_b nConfig FPGA input When asserted (i.e. when it goes low - this is an active low pin), the FPGA is reset-ed and looses its configuration. If the FPGA was in user-mode, it stops operation immediately, and all IOs become inactive.
init_b nStatus FPGA output This pin indicates when the FPGA is ready to start the configuration process (it takes a few milliseconds for the FPGA to get ready).
done ConfDone FPGA output When high, indicates that the FPGA is configured (i.e. in user-mode).

Note: the init_b and done pins are actually open-collector pins, so pull-up resistors are required on these. Also if multiple FPGAs are to be configured, these pins are usually connected together so that all the FPGAs switch into "user-mode" together. There is many more details, so for a complete description, check your FPGA datasheet.