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Spoc main characteristics

Spoc was designed to be almost free, i.e. to consume little space in the FPGA, and to execute from a serial flash memory. Many new FPGA boards have a serial flash already used to configure the FPGA. Spoc can use the unused memory space of the Flash as code memory.
Spoc can be parameterized.
For now, the first implementation, "Spoc0", is not.

Spoc0 has the following fixed characteristics:
How fast is Spoc0?

Of course, that dependends of your clock speed and what type of instructions you are running... but even at 100MHz, Spoc0 is probably slower than other available CPUs.

CPUSize (1)Clock speed (1)MIPStargetNative data sizes
Spoc0175 slices/300 LEs100MHz2 to 5 (estimated)Any FPGA/ASIC1, 8, 16 and 32 bits
Microblaze1000 LEs ???Xilinx FPGA32 bits
Picoblaze100 slices ???Xilinx FPGA8 bits
Nios II700 LEs ???Altera FPGA32 bits
(1) Xilinx Spartan 3 or Altera Cyclone 2, slowest speed grades
Note: table provided without any guaranty of accuracy or fairness (comparing different CPUs fairly is difficult)

While designing Spoc0, the goal was not to get the fastest possible CPU, but a small (low logic-usage) CPU efficiently targeted for today's FPGAs (and ASICs).
In the CPU world, speed and logic usage goes in pair. Fast CPUs use inherently wide buses - which increase their logic usage. Spoc0 takes the opposite approach and trades bus width to clock cycles. In other words, Spoc0 serializes many of its tasks (it uses more clock cycles per instructions) but stays slim. In the future, some tasks could be optionally parallelized - at the cost of a higher logic usage.