Spoc main characteristics
- Small logic usage
- Generic architecture, runs easily in Xilinx and Altera FPGAs. Could easily be ported to ASIC too.
- RISC:
- Small instruction set
- Multiple accumulators, multiple data sizes
- Dual register file
- Conditional execution in each instruction
- Data memory: uses (at a minimum) one blockram
- Code memory: uses either a serial flash, or a blockram
Spoc was designed to be almost free, i.e. to consume little space in the FPGA, and to execute from a serial flash memory.
Many new FPGA boards have a serial flash already used to configure the FPGA.
Spoc can use the unused memory space of the Flash as code memory.
Spoc0
Spoc can be parameterized.
For now, the first implementation, "Spoc0", is not.
Spoc0 has the following fixed characteristics:
- 4 data sizes/accumulators: 1, 8, 16 and 32 bits
- 2 register files of 32 registers each, each register is 16 bits wide
- 64Kbits of data addressing space
- 64Kbits of code addressing space
- Uses a minimum of 2 blockrams (one for data space, one for code space)
- About 300 lines of Verilog
- Maximum clock speed in the 90-110MHz range (Spartan 3/Cyclone 2, slowest speed grades)
- Logic usage, about 175 slices/300 logic cells (Spartan 3/Cyclone 2).
How fast is Spoc0?
Of course, that dependends of your clock speed and what type of instructions you are running...
but even at 100MHz, Spoc0 is probably slower than other available CPUs.
| CPU | Size (1) | Clock speed (1) | MIPS | target | Native data sizes |
|---|
| Spoc0 | 175 slices/300 LEs | 100MHz | 2 to 5 (estimated) | Any FPGA/ASIC | 1, 8, 16 and 32 bits |
| Microblaze | 1000 LEs ? | ? | ? | Xilinx FPGA | 32 bits |
| Picoblaze | 100 slices ? | ? | ? | Xilinx FPGA | 8 bits |
| Nios II | 700 LEs ? | ? | ? | Altera FPGA | 32 bits |
| ... | . | . | . | . | . |
(1) Xilinx Spartan 3 or Altera Cyclone 2, slowest speed grades
Note: table provided without any guaranty of accuracy or fairness (comparing different CPUs fairly is difficult)
While designing Spoc0, the goal was not to get the fastest possible CPU, but a small (low logic-usage) CPU efficiently targeted for today's FPGAs (and ASICs).
In the CPU world, speed and logic usage goes in pair.
Fast CPUs use inherently wide buses - which increase their logic usage.
Spoc0 takes the opposite approach and trades bus width to clock cycles.
In other words, Spoc0 serializes many of its tasks (it uses more clock cycles per instructions) but stays slim.
In the future, some tasks could be optionally parallelized - at the cost of a higher logic usage.
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This page was last updated on October 22 2005.