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russdx
Joined: 13 Mar 2010 Posts: 7
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Posted: Sat Mar 13, 2010 11:14 pm Post subject: Configuring FPGA boot rom causes program to run half speed |
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when i configure my FPGA (Xylo) normally, It runs the correct speed (24mhz) yet if i configure the boot prom with the very same rbf it will run half speed on start up (12mhz)
any ideas on what i may be doing wrong? (iv noticed you can set the fx2 clk speed 12/24/48, its like even though this is set to 24 when i program the boot prom it resets it self to 12mhz)
im using the FPGAconf 2.12.02
any help would be greatly appreciated as my project is now ready to be run stand alone without a usb umbilical cord connected to it and would be great if it ran 24mhz when it starts up  |
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fpga4fun Site Admin
Joined: 18 Sep 2003 Posts: 825
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Posted: Sun Mar 14, 2010 1:23 am Post subject: |
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12MHz is the native speed of the board but you can change it by adding an EEPROM to the FX2 and programming it with this file from the StartupKit.
"EEPROM FX2 change startup clock to 24MHz.bin"
Check also the doc chapter 21. |
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russdx
Joined: 13 Mar 2010 Posts: 7
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Posted: Sun Mar 14, 2010 12:38 pm Post subject: |
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I see
When i do a search for I2C devices nothing shows up / Trying to program the I2C EEPROM just gives an error
I did notice in the documentation it mentions the FPGA must be configured with a “soft macro” I2C controller.
I could not find any example rbf files to do this. |
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fpga4fun Site Admin
Joined: 18 Sep 2003 Posts: 825
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Posted: Sun Mar 14, 2010 2:21 pm Post subject: |
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| It has nothing to do with a soft macro I2C controller, what is missing is an I2C EEPROM, you have to either solder one on the board or connect one to the I2C connector. Then you can program it. |
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jasimpson
Joined: 27 Jun 2007 Posts: 5
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Posted: Tue Aug 10, 2010 12:33 am Post subject: |
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I'm trying to do the same thing, except I'd like to set the default to 48MHz.
Can you provide a "EEPROM FX2 change startup clock to 48MHz.bin" I2C EEPROM bin file that I could use for this purpose?
I'd really appreciate it. Thanks.
PS I would use the PLL, but the PPL is already being used to generate two other clocks with speeds incompatible with 48MHz. |
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fpga4fun Site Admin
Joined: 18 Sep 2003 Posts: 825
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Posted: Tue Aug 10, 2010 5:57 am Post subject: |
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| Send a request to KNJN, they might have the file you need. |
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