fpga4fun.com

[weiman]

[surge_me]

Hello All,

I made an FX2 (cypress chip) usb blaster. If I plug it into the computer and donwload the software from kawk (witht the PID and VID edited), it shows up as an Altera USB blaster and installs the apropriate drivers.

So far so good.

The problem is that once installed, Quartus does not recognize the cypress chip as a usb blaster....

So is this a known error? or did I do something wrong?

Some info: I use SDCC, to compile the software from kawk.
I use the make file in the device\c51 file and I load the std.hex file in the processor
I also use the cygwin implementation of 'make' in a windows command prompt to make the hex file.

[kawk]

Hi,

Quartus will detect the device as an "USB-Blaster" (tm) only if the product description <b>string</b> says it is one. That's even more important than the PID/VID.

The speed of the FX2 variant is about 60% compared to the FTDI variant.

The only tools that will work with the usb_jtag VID/PID 0x16C0 are openwince JTAG tools (resp. the new UrJTAG fork of it) and OpenOCD with a patch I posted some time ago in their Forum. Both can be compiled for Windows as well.

Regards,
kawk

[mr alex]

Hello everybody,

I am a newbie in PLD and I wish to make an "USB-Blaster" compatible cable and a "Platform Cable USB" for xilinx devices (I have some altera and xilinx cpld). I already have some cy68013a chips.

The problem is that I don't understand very well what you say on previous pages.
Where can I find a schematic ?
How can I program the cypress chip ? (Does it remember the program code?)

Thanks guys

[kawk]

Hi,

For the USB-Blaster compatible cable you take a FX2 and load the firmware from my usb_jtag project to it, temporarily - it'll forget it after unplugging. It is possible to put it into an EEPROM attached to the FX2 though. You'll have to modify the firmware with Altera ID codes if you want to use it with Altera software. It doesn't come with that out of the box.

It is not possible to build a Xilinx compatible cable with my firmware. It is however possible to load the firmware on a Xilinx cable so that it behaves like an Altera cable.

Well, having a compatible cable is very convenient. However, if you just want FPGA configuration and don't want to use vendor specific functions (like SignalTap logic analyzer and JTAG UART in Altera logic, or similar with Xilinx), you don't need a vendor-compatible cable. You can build one e.g. based on FTDI's FT2232 and use software like UrJTAG or OpenOCD or others for downloading the configuration to the target. But if that looks like an option to you, I recommend to start a separate thread about it.

Kolja

[mr alex]

ok, thanks Kolja.

So I think I will start to build the board in order to work on it (try to build...).

I will connect like that:
PD4/FD12 (pin 56) = TMS
PD2/FD10 (pin 54) = TDI
PD1/FD9 (pin 53) = TDO
PD0/FD8 (pin 52) = TCK

It would seem that Urjtag and OpenOCD does not function on Windows.
How can I do on windows ?

Alex

[beattie]

I'm having a problem using openocd to talk to my saxo-L under Linux. Any advice of clues would be helpful.

I grabbed Kwak's zip file and the svn sources for OpenOCD.
I patched and built openocd.
I built the std.hex file with "make HARDWARE-hw_saxo_l" and fxpush.
I loaded the std.hex file and ran openocd using the config file below.
I'm getting the following errors:

[beattie]

I have made no progress, though I did build a WinXP system and tested the Saxo-L on it and everything works, OpenOCD talks to the ARM and fpgaconfig loads the FPGA.

I also tried ur-jtag under Linux and it can't talk to the board either. I found links to the earlier usbjag sources, but I don't have the Keil compiler needed to build that version so I can't check it.

Trying to debug this with-out a working example I can look at or schematics/pin-out is difficult.

Would it be possible to get the source for the current windows driver or partial schematics?

--- update: looking at the board it looks like the FPGA TDI, TDO, TMS, and TCK are connected to Port D bits 0, 1, 2 and 3 respectively. This agrees with the software I have so it would seem to not be a simple configuration issue, though I confused by the fact that both TDO and TDO are connected to the same chip, I must not understand JTAG unless there are two JTAG chains on the Saxo-L or there is some magic going on.

Anyone have an clues they might wish to share?

[sunemai]

Hi all!
I've modified Kolja's FX2 code to work with an FPGA development board called NEXYS from Digilent Inc. (they come with FX2 firmware pre-loaded, but I want some different features from their default).

Board layout: 56 pin Cypress FX2 drives the JTAG chain consisting of Xilinx Spartan XC3S1000 FPGA (part 1) and Xilinx xcf04s (part 0) configuration ROM.

Port assignments: FX2, port D drives JTAG chain and controls FPGA power on.
The default firmware uses port A and B to emulate an EPP port. In addition to the JTAG part, I want my new firmware to implement a WISHBONE interface, ideally configurable as either master or slave interface, or both.

So far I have the JTAG part _almost_ working:
Changes from Kolja's code are mostly the port assignments, power on etc.:
TCK = D.4
TDI = D.2
TMS = D.3
TDO= D.0
USBPOW = D.7 (turns on board power from usb)
USBJTAG = D.5 (when high, the FX2 can drive the JTAG chain.)
Output enables are changed from OEC to OED corresponding to the above ports.

From the UrJTAG promt I can load "cable UsbBlaster" and detect the xcf04s and the xc3s1000 ( after adding "1111 xcf04s 15" to the UrJTAG STEPPINGS file for the xcf04s). Print chain also works without errors in UrJTAG.

But: When I load a design using "part 1", "svf mydesign.svf stop progress" the FPGA is not configured correctly. Loading the same svf-file onto the same board using a parallel JTAG cable, the design works as intended (it blinks a led...), so the FPGA is not broken.

Any suggestions on how to debug this situation? The FPGA's "configuration done LED" lights up after the svf command, and no errors are reported by the svf command, only a warning about the USB-blaster frequency being fixed to 12MHz. Is this really an error with the UrJTAG svf command, or could I be missing something?

Best regards
Sune Mai

[sunemai]

I'll try to clarify my questions:
UrJTAG + DLC5 Parallel cable :
JTAG chain detect + FPGA config from SVF file works perfectly!
UrJTAG + UsbBlaster/FX2 firmware :
JTAG chain detect works perfectly but FPGA config from same SVF fails.

How is this possible? If my mods of the FX2 firmware are buggy, shouldn't the JTAG chain detection fail as well?
\Sune Mai

Update: Adding a STAT register readback to check the FPGA status after configuration shows that the _only_ difference between the (working) parallel cable load and the (not working) FX2 load is bit 7 of the STAT register, GHIGH_B. The Spartan-3 STAT register bits are thus
parallel cable:
00110111101110... (the rest, bit 14-31, are zeros as they should be).
With FX2 firmware:
00110110101110...
There are thus no CRC errors during the load, the DONE signal goes high, indicating a successfull load in both cases, etc. Time to investigate what GHIGH_B means...

Suggestions are still very welcome - this could be an issue for all users experiencing a "Load OK, but design not working" type of problem with kawk's FX2 firmware (not that I can say, that the problem is in the firmware, of course...)

[sunemai]

Fixed it. See
http://sourceforge.net/forum/forum.php?thread_id=2312452&forum_id=682993
for details.

[duddface]

Hi Kolja,
Good work. I have a Xylo-LM and was wondering if this can be adapted to my Xylo board that has the Spartan XC3s500E FPGA in it? If so, how would i go about it?

thanks in advance,
Ananth

[blipton]

Hi,

With the day off (Yay Labor day!) , I thought I'd play with the USB JTAG adapter code posted.. we are always short @ltera usb blasters in the school labs so this could be very handy!

Anyways, I have an FTDI245BM chip with the vendor/id/driver configured as a real usb-blaster... connected to a cpld running the jtag_logic.vhd downloaded from http://www.ixo.de/info/usb_jtag/. For testing, I have the jtag from the cpld going to an old flex10k board.

The problem is that while Quartus sees a usb-blaster ok, it cannot detect the flex10k or the jtag chain.

As far as I can tell, when I click auto detect in Quartus, I do see activity on the tclk line, but I see no activity on tms or tdi. The 8 data lines and control signals (rx,tx,rxf, txe) between the 245bm and the cpld seem to be toggling as well.

I've used the flex10k board with a real @ltera usb blaster so I know it's jtag chain is good... however, just to isolate the cpld jtag, I disconnected it from the flex10k board. I still do not see any activity on tms or tdi, so it not like it's being held down.

Any ideas what would could be causing the problems? I looked into the jtag_logic state machine, but didn't see any output debug signals that I could monitor.

[tweakoz]

I bought two of these:
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&Item=200448628882&Category=16145&_trkparms=algo%3DLVI%26its%3DI%26otn%3D2#ht_4226wt_939
and they have 14pin xilinx jtag ports on them.

And I am tempted to buy one of the USBFX2-JTAG programming boards at
http://www.knjn.com/ShopJTAGcables_USB.html
and use the kawk firmware.

My question is how do interface a xilinx 14pin jtag port to it?
Is there a premade cable I can buy ?
If not what connections do I need to make?

thanks,
mtm

[haukex]

Hi all,

I just wanted to let everyone know that Kolja's firmware is now hosted on SourceForge:

http://ixo-jtag.sourceforge.net/

Also, I am curious who is using this firmware? I just would like to know if the firmware files are still current

Thanks,
-- Hauke D

[plaressa]

Can I use a regular usb cable to connect a broadband modem to my wii? Some of Comcast's modems have a usb port on them, and I was just wondering if it's possible to run a hardline connection from the modem to the Wii just using a regular usb cable instead of buying one of those usb-to-ethernet lan adapters. Any help would be appreciated. Thanks.
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