fpga4fun.com

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

I got it to work!
I found that I had to remove the @echo command...

kawk · Joined: 23 Apr 2006 Posts: 13

Strange - the first echo fails, the second one works? Probably Make tries the first one as an executable, the second one through a shell...

Just yesterday I found a way to make a proper libfx2.lib that doesn't depend on any external tools. GNU Make itself supports archives:

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

I'm not sure which files I need to modify to try on one of my boards.

hw_basic.c
I probably have to set all the defines to 0
#define HAVE_PS_MODE 0
#define HAVE_AS_MODE 0
#define HAVE_OE_LED 0
and overwrite the sbit definitions, and update the ProgIO_Init(void)

hw_xpcu_i.c
Do I have to also update the defines?
Also have #define HAVE_OE_LED 0 instead of 1

hw_xpcu_x.c
Use #define HAVE_OE_LED 0 ?

usbjtag.c
In void usb_jtag_init(void), I need to change the EPxCFG settings.

kawk · Joined: 23 Apr 2006 Posts: 13

Hi,

The hw_basic is basically the original code. I suggest you change only the definitions at the top of hw_basic.c.

Copy hw_basic.c to hw_xylo.c (or whatever you want to name it) and put this in the top of the Makefile or run "make" with argument "HARDWARE=hw_xylo":

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

I created an hw_saxo_l.c file, commented the first 3 defines, and updated the sbit definitions. I also updated the void ProgIO_Init(void) (I don't use portE for power, and I use portD instead of portC)

In usbjtag.c, I changed all the EPxFIFOCFG to 0x04, so that portD can be used as IO.

I also changed dscr.a51 to simulate a USB-Blaster. Maybe that's where I screwed up, the board beeps three times after re-numeration.

klingler · Joined: 09 Apr 2007 Posts: 3

So..what is the actual status of the Cypress FX2 solution now?

Is it really recognized as USB Blaster under Quartus?
And how about firmware loading under Windows?

I have ordered some FX2 samples from Cypress and will make an opensouorce schematic and PCB design so others can benefit as well...

cheers
rick

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

Sure it works great, you can make the FX2 look like a USB-Blaster.
Firmware loading is done through a Cypress utility that you can download from Cypress website.

klingler · Joined: 09 Apr 2007 Posts: 3

Kuul (o;

And you used the TSOP56 package as well I saw...
Have you any difference besides pinout from the original code?

So I guess it's time to do schematic and layout...
good excersize to see if PADS2007 evaluation version is
enough for this...

cheers
rick

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

I had some code differences but I posted them in this topic. It was due to the different ports I am using.

klingler · Joined: 09 Apr 2007 Posts: 3

Just received my ECP2 Mico32 board today from Lattice...

And what they're using for USB programming? The CY7C68013A of course, but with a MachXO in between (o;

Oh...Cypress also deliverd 3 CY7C68013A samples which I ordered 2 nights ago (o;

cheers
rick

Dweil · Joined: 09 May 2007 Posts: 1

Hi!

I'm currently also building this great project, with the FTDI chip and the CPLD. The problem is: Quartus hangs when I plug in the home-brew USB blaster. Can someone tell what what I am doing wrong? I already checked all connections, verified the CPLD (I'm using a 7064AETC-44) My target is a Pluto 3 board.

I hope you can help me.

Danny.

outer_space2 · Joined: 09 Oct 2005 Posts: 51

Does this software let you program the xylo fpga over fx2 usb?

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

Yes, it does, although on Xylo, a modification is required (4 wires to solder).

outer_space2 · Joined: 09 Oct 2005 Posts: 51

So I can program and debug if I do this modification, otherwise I can only program? I'll look closely at this code before asking which 4 wires go where.

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

Yes, it makes the FX2 simulate a USB-blaster, so you can control the FPGA from Quartus.
Quartus has SignalTap, which allows to get a virtual logic analyzer inside the FPGA - very nice!

jsteele · Joined: 29 Jun 2007 Posts: 5

Hi, I have a new Xylo-L board, and I would like to use the usb_jtag software with it. I have read through this thread and have a few questions.

1) On the Xylo-L board, are the JTAG connections the same as mentioned previously ? i.e.,

port D.4 = TDI
port D.5 = TCK
port D.6 = TDO
port D.7 = TMS

2) If so, shouldn't the ports be enabled, instead of the FIFO in the IFCONFIG register ?

i.e., IFCONFIG = 0

In one post you (fpga4fun) had IFCONFIG=3, which would disable port D.

3) On the Xylo-L board, does this JTAG chain include both the Spartan3 FPGA and the LPC2132 ARM CPU ? Which one comes first ?

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

Actually there are two JTAG chains on Xylo-L, one of the FPGA and one for the LPC.

The port D and the FIFO can be enabled together, because Xylo-L uses the FIFO in 8-bits mode, so port D is free.

Do you want to use usb-JTAG with the FPGA or with the LPC?

jsteele · Joined: 29 Jun 2007 Posts: 5

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

Looks good.

sewsew · Joined: 22 Aug 2007 Posts: 2

Hello guys.

Im trying to make a custom USB-JTAG Board using the FX2, and i have some problems with it.

My pc views perfectly the FX2 as an ALTERA-BLASTER, after i uploaded the firmware etc.

When i run Quartus, and i start to detect (into the Hardware Setup into the Programmer Window), Quartus does not respond, it becames "time out", and i have to finish the program with the task manager.

But if i try with the evaluation board (SAXO-L rev.A), Quartus works perfectly.

Well, i don't know what i am doing wrong with the FX2.

I tried with and without EPROM (the pull-up resitors are always on at the I2C pins).

All the GNDs and VCCs are connected, the USB wires are ok, and i am using the PD0...PD3 like the original board.

There aren't shortmakes, my board is not damage... just i checked all the electrical parts, and everything is ok.

Well hehe, i am open for everything.... thx guys for your answers

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 828

Make sure the FX2 pin WAKEUP is high. It's probable not the reason, but it is high on Saxo-L.

sewsew · Joined: 22 Aug 2007 Posts: 2

Yes, thx for your quick answer.

WAKEUP is HIGH and RESERVED is GROUND.

Any special config for talk over the PD0...PD3 ?

Im using an external 24MHz clock too (I use only the clk IN). The Saxo is using a resonator one using boths.

guopo · Joined: 05 Sep 2007 Posts: 1

Kawk, Thanks for your great work!!

Now, I changed source code as fpga4fun did and work well. I changed VID,PID (09FB, 6001), so it can be renumerated as usb-blaster. I saw you said that it can be usb-jtag-if have its own VID PID, but i can't find any driver for windows. so if i use your VID,PID, how can setup device?

Thanks!

outer_space2 · Joined: 09 Oct 2005 Posts: 51

I know this is probably a 'no' but is it technically possibly to port this to a usb 1.1 chip?

Lonsn · Joined: 15 Oct 2007 Posts: 1

I want to know about the bit download speed using FX2 usb-jtag (Compared to using FTDI chips).
Thanks!