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kawk · Joined: 23 Apr 2006 Posts: 13

Hi,

you might find my FX2 firmware interesting that implements a different style of USB-JTAG communication. It's made for another board that also has a FX2 for communication with an Altera FPGA, but adapting it should be easy:

http://www.ixo.de/info/usb_jtag

K.

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

Looks very interesting. Thanks for putting that online. I just looked at the CPLD code and it seems pretty straighforward. It seems from your comments that you worked more on the FX2 than the CPLD. Was the CPLD tested in hardware?

I also digged into the FX2 code. I'm trying the code as-is, although I'll have to change the PortC to something else (I'm using the 56 pins version of the chip) and I'll want to simulate an FTDI chip eventually.

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

Ok, getting very close. I'm trying to see if I can get the USB-Blaster emulation working.

I had a problem that the board would not re-enumerate. I had to add this line to the TD_Init routine.
Rwuen = TRUE;

Now it re-enumerates (most of the time... sometimes it doesn't, will have to work on that later) and asks for a driver. Next was to update the descriptor and EEPROM files... not sure if I got that 100% right but Quartus detects a USB-BLASTER!

Next I updated the PortC to PortD in the code, with the right pins for my board, wasn't too hard. Now I don't see any activity on the JTAG lines... and Quartus says "Can't access JTAG chain". But hopefully I'm close.

CMOS · Joined: 21 Dec 2003 Posts: 7

This one is much simpler http://www.ftdichip.com/Projects/MPSSE.htm#JTAG

kawk · Joined: 23 Apr 2006 Posts: 13

Hi,

I assume there's still something with the pin assignment and I/O configuration that causes the "Can't access JTAG chain" problem. You should at least be able to see some activity on the TCK and TMS pins when you try "Auto-detect" with the Quartus Programmer. Maybe the Output Enable definition (OEC=...) in line 128 of usbjtag.c? Assignments to adapt are:

usbjtag.c in lines 42..49 and 128 (OEC=...). There are some lines specific to my test hardware, e.g. the VCC for the FPGA has to be turned on by activating PortE lines - these aren't needed and might in fact cause unwanted side effects on your hardware?

shift.a51 in lines 24..27.

The FX2 code has now been tried on three different boards, but none of them is using the small (56pin) version. However AFAIK there is no major difference that would prevent the code here from working on the smaller one. Thanks for anything you discover!

The CPLD code really was tested in hardware; I'm using it to debug my attempts to port the RTEMS operating system to NIOS2 on this setup:

http://www.ixo.de/info/usb_jtag/eb2_usbjtag_eth.jpg

The board with the usbjtag to the right is a LiveDesign Evaluation board (Cyclone Edition) from Altium. The FT245BM on the usbjtag came to me as a module made by another hobbyist - that was by far the fastest way to get something working. The board at the bottom of the picture is a PCI Ethernet card from which I removed the "PCI" part (a DEC21140 MAC)... the PHY chip on it is now wired via level shifters to the FPGA with an OpenCores.org Ethernet MAC inside.

Good luck, K.

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

It seems that the WAKEUP pin should be high for the re-numeration to work reliably. I also found why my IOs weren't toggling (I'm using PD8..15 so I had to put FD in 8-bits mode) - now I can see IO activity when Quartus detects the JTAG hardware. But Quartus hangs there. Probably another small mistake somewhere.

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

Found the mistake - this thing works!

kawk · Joined: 23 Apr 2006 Posts: 13

Glad you have it working!

If you send me your final diffs to usbjtag.c/shift.a51, I'll put that in
the README as "patches for Saxo/Xylo" or the like. Or you could just
describe it online here.

I'll now concentrate on drivers for this (and compatible...) devices in other JTAG projects such as openwince-jtag. Further interesting things to find out: if Altera software can be used with it without tweaking of USB IDs? How does communication with JTAG UARTs in SOPCs work? Adapting jrunner should be easy, but I'd like to have something like nios2-terminal ...

K.

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

The FX2 is amazing, being able to emulate a USB-Blaster (FTDI + CPLD) with a completely soft solution.

I tried your files on Saxo/Xylo. I used the PortD instead of PortC, the changes are shown below. Feel free to include them into your file distribution.

I found that the EEPROM content is not required (EEPROM.c file) and the content can be replace by all 0's.

In usbjtag.c, put
sbit TDI = 0xB0+4; // high nibble of PortD
sbit TDO = 0xB0+6;
sbit TCK = 0xB0+5;
sbit TMS = 0xB0+7;
#define bmTDIOE bmBIT4
#define bmTDOOE bmBIT6
#define bmTCKOE bmBIT5
#define bmTMSOE bmBIT7
...
IFCONFIG = 3;
EP2FIFOCFG = 0x04;
EP4FIFOCFG = 0x04;
EP6FIFOCFG = 0x04;
EP8FIFOCFG = 0x04;
OED = bmTDIOE | bmTCKOE | bmTMSOE;
// remove any reference to PortE
...
BOOL DR_VendorCmnd(void)
{
if(SETUPDAT[1] == 0x90) // READ EEPROM
{
EP0BUF[0] = 0; // EPROM content is actually not required
EP0BUF[1] = 0;
...

In shift.a51, use
TDI BIT 0B0H+4H
TDO BIT 0B0H+6H
TCK BIT 0B0H+5H
TMS BIT 0B0H+7H

Finally if you want to emulate the USB-Blaster, you can change the dscr.a51
dw 0FB09H ;; Vendor ID 0x09FB
dw 00160H ;; Product ID 0x6001
and update the StringDscr2 to "USB-Blaster" (vendor can be anything)

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

I'm not sure how good is the FTDI solution with their "Multi-Protocol Synchronous Serial Engine (MPSSE)"
http://www.ftdichip.com/Projects/MPSSE.htm#JTAG

But I like the idea of using an FX2 - it's soft so very easily upgradable.

As for the SOPC JTAG, that's proprietary Altera. Too bad because they have a good JTAG solution compared to Xilinx. SignalTap is superior to Chipscope too in my opinion (better integrated to their software suite).

cypher101 · Joined: 10 Jun 2006 Posts: 1 Location: Dublin

Would I be correct in saying that the JTAG pins of the FPGA are not connected to the FX2 on the Xylo boad at present?
I recently purchased the Xylo and I wouldn't mind giving this USB-Blaster firmware a shot...

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

Yes, you have to solder 4 wires from the FX2 chip to the JTAG connector. I used the FX2 pin 56, pin 1, 2 and 3 (PortD) as you can deduct from the code above.

Also make sure WAKEUP is high (there is a resistor strap option on the back of the board).

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

The new Xylo-EM board (announced today) is pre-wired for this project, no need to solder the 4 wires anymore!

I kept the JTAG connector, for those you still want to use an external JTAG cable (or for those who need to use JTAG & USB-2 at the same time).

romlum · Joined: 28 Jul 2006 Posts: 2

Hello,

I am a student working for an university. We want to develop
the same firmware (USB-JTAG connection) for an home-made Altera Cyclone2 board.

We want to replace the Altera USB-Blaster solution by an FX2 directly connected to the JTAG ports of the FPGA.

I just have some questions about your solution FPGA4Fun. Please,
can i contact you or could you give me your whole project?

THANK YOU.

romlum · Joined: 28 Jul 2006 Posts: 2

Finally it works Smile

, it was just a problem of cable connectic

kawk · Joined: 23 Apr 2006 Posts: 13

Hi,

I've rewritten the usb_jtag firmware, because I needed a version that can be compiled with SDCC instead of Keil. It's now based on USRP code from the GNU Radio project.

The hardware-specific part is somewhat better separated from the main code. If you prepare hw_xylo.c/h files for the boards here, I'd include it in the next release.

Kolja

http://www.ixo.de/info/usb_jtag/

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

Will do. I'm quite busy with my new ARM board so I'll do it in a little while.

I see that you are playing with the Xilinx Platform Cable USB now. Too bad this one has a CPLD, but I guess it allows faster JTAG communication.

kawk · Joined: 23 Apr 2006 Posts: 13

Yes, I was just curious about the XPCU and whether I could run my firmware in it. The CPLD is attached to the FX2 GPIF with 16 bit data bus, so it is possible to use the USB with real high speed transfers (480 MBps).

In my newest firmware, I just utilize the most basic CPLD access waveforms (one JTAG pin state change per trigger) that allow me to bit-bang the external JTAG chain, well, for a proof-of-concept "X-Blaster".

More complex waveforms seem to allow transfer of multiple data bits at once to/from parallel/serial converter, and there are several versions of the same basic waveform for different JTAG clock speeds. Probably up to IFCLK/2...

But I think I find enough spare time to find out how to utilize those faster speeds.

The hardware is much more flexible and faster than an FT245+CPLD solution but cheaper than an USB Blaster (USB150 vs USB-Blaster at USD300?!)...

Kolja

kawk · Joined: 23 Apr 2006 Posts: 13

Hi, I've simplified the code; the board-specific part has been restructured. New ZIP available at http://www.ixo.de/info/usb_jtag/. Now I consider this structure "stable"... Kolja

outer_space2 · Joined: 09 Oct 2005 Posts: 51

Is it ok to use SDCC to compile FX2 usb firmware? Or is there some reason to use the evaluation compiler?

kawk · Joined: 23 Apr 2006 Posts: 13

Hi,

Use SDCC for the new firmware (in "c51" subdirectory). It won't compile with Keil at all. Keil must be used for the older firmware (in "fx2.old" subdirectory), but I don't support that version anymore. I use SDCC 2.6, as shipped with Ubuntu 6.10.

Kolja

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

I tried on Windows and run a make. Got a "basename: command not found"... I guess I need to install cygwin.

kawk · Joined: 23 Apr 2006 Posts: 13

fpga4fun · Site Admin Joined: 18 Sep 2003 Posts: 820

Almost, now I get a "C:\Program: C:\Program: No such file or directory"
It may not like a path with spaces.

kawk · Joined: 23 Apr 2006 Posts: 13

Well, the result shall be a file "libfx2.lib" with simply the names of all objects without ".rel" extension: