32-bit Dadda or wallace tree Multiplier VHDL code

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32-bit Dadda or wallace tree Multiplier VHDL code

Postby mml » Tue Aug 25, 2009 9:12 am

Hello
I work on my thesis and I want to simulate 32-bit Dadda or wallace tree multiplier, but I can not write VHDL code very well.

please help me on my problem.
thanks.
mml
 
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Joined: Tue Aug 25, 2009 9:07 am

Postby bluemind » Tue Aug 25, 2009 4:08 pm

it is not that hard.

it goes like this
1. deside the Radix - 2,4,8, ore even 16
2. Make the encoder
3. Make the partial product generator
4. Deside the structure of the walles tree or Dadda(what ever that is)
5. make the adder structure of general blocks
6. either generate a final addition ore used a generic adder

that is it...... you thesis is finish
bluemind
 
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