How to analyze Timing summary in ISE

Anything about FPGA boards, like how to assemble SMD components, find low-voltage regulators, FPGA configuration...

How to analyze Timing summary in ISE

Postby anch » Thu Apr 22, 2010 9:08 pm

Hi, I am getting following timings of my design. i dont know exactly how to set clock low and high time by using following information. Please help me regarding this.

Minimum period: 31.540ns (Maximum Frequency: 31.706MHz)
Minimum input arrival time before clock: 5.326ns
Maximum output required time after clock: 13.804ns
Maximum combinational path delay: 11.719ns
anch
 
Posts: 9
Joined: Thu Oct 29, 2009 5:28 pm

Return to General boards

Who is online

Users browsing this forum: No registered users and 1 guest

cron