you are trying to write hardware like a piece of software: do this and this and then do that (sequentially). In VHDL your hardware has a current state (content of your signals and sometimes of your variables) and you have to describe how to come to the next state, which is only an infinite small amount of time in the future.
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if rising_edge(clk) then
does not mean "wait here until the next rising edge comes", it means "if the current state is a rising edge". So if there is no rising edge, your code will end in an endless loop, because there is no time increment while your code is processed.
Try to simulate your code, it should help you understand what you have written.
(This is the most obvious error)