Implementing a FSM in VHDL

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Implementing a FSM in VHDL

Postby Rigby » Sat May 14, 2011 11:11 am

Just wondering if I'm implementing a finite state machine in VHDL whether or not I need to state what **all** of the outputs are in every possible state? Even if I know that some outputs won't change from one state to the other and I know that the order of the states will also be in the same order?

For example, in this (forced) example:

Code: Select all
entity test is
       port (
          clk : in std_logic;
          a : in std_logic;
            b: out std_logic;
            c: out std_logic;
       );
    end test;
   
    architecture Behavioral of test is
   
    type executionStage is (s1,s2,s3);
    signal currentstate, nextstate: executionStage;
   
    begin
       process (clk)
       begin
            if(rising_edge(clk)) then
                 currentstate <= nextstate;
            else
                 currentstate <= currentstate;
            end if;
       end process;
   
        process(currentstate)
       begin
            case currentstate is
                when s1 =>
                    if (a = '1') then
                        b <= '1';
                        c <= '0';
                    else
                        b <= '1';
                        c <= '1';
                    end if;
   
                    nextstate <= s2;
   
                when s2 =>
                    -- b doesnt change state from s1 to here, do I need to define what it is here?
                    if (a = '1') then
                        b <= '1';
                        c <= '1';
                    else
                        b <= '1';
                        c <= '0';
                    end if;
                   
                    nextstate <= s3;
               
                when s3 =>
                    iif (a = '1') then
                        b <= '0';
                        c <= '0';
                    else
                        b <= '1';
                        c <= '1';
                    end if;
                   
                    nextstate <= s1;
            end case;
        end process;
    end Behavioural;
               



From my understanding if I don't do this then latches are created?

It's not a big deal in something like that example but if I have a machine with more than 10 outputs and more than 10 states then my VHDL files start to look incredibly messy and I'm sure it must be bad practice to copy and paste the same thing over and over. Is there a better way of doing this?

edit: Can I define a 'default' state for an ouput? IE set b to be 1 outside of all the processes and then only define what it is in the case statements where it is 0? Would that work?
Rigby
 
Posts: 1
Joined: Sat May 14, 2011 11:09 am

Re: Implementing a FSM in VHDL

Postby hamster » Mon May 16, 2011 12:09 am

Hi,

If you don't state what all outputs will be for each state, then the output will hold it's last assigned value. Sometimes this is what you want, and sometimes it isn't.

You also need to be careful about 'hazards' if you have your output is implemented as combinatorial logic (because you have specified the output at all FSM states) it won't have a flipflop holding the value. This will give transient glitches following the clock edge as the signals settle down into a stable state. Usually this can be ignored for synchronous systems, but can really upset any async external components.

It is very real issue - in a 1440x900 (106MHz) VGA display I was playing with this gave "ghost" edges where complex logic controlled took a few ns to decide on a pixel's value. At least I could see it and I was able to add flipflops to clean the output. I would hate to see what would have happened if that was the "CS" to a DRAM chip - would have been almost unsolvable.

One other technique I have seen is to make the signal that holds the FSM state a larger vector than it needs to be (or carefully assign values to each state) and then use the extra bits to drive external control signals. This usually ensures glitch-free outputs and requires minimal extra resources, but does require a bit more design work up front.
hamster
 
Posts: 53
Joined: Mon Sep 27, 2010 10:19 pm

Re: Implementing a FSM in VHDL

Postby tricky » Wed May 25, 2011 2:04 pm

Rigby wrote:From my understanding if I don't do this then latches are created?

It's not a big deal in something like that example but if I have a machine with more than 10 outputs and more than 10 states then my VHDL files start to look incredibly messy and I'm sure it must be bad practice to copy and paste the same thing over and over. Is there a better way of doing this?

edit: Can I define a 'default' state for an ouput? IE set b to be 1 outside of all the processes and then only define what it is in the case statements where it is 0? Would that work?


Correct - and in FPGAs latches are BAD.

You can define a default state. At the top of the process just write:

output <= '0'; --or whatever your default value is.

In VHDL, signals take the last value assigned to them, so in this case output will be '0' unless something else is assigned.

The best solution to al of this is not to use a 2 process state machine. If you define the state machine in a single clocked process, all of your outputs will be registers anyway, eliminating any possible latches.
tricky
 
Posts: 58
Joined: Wed Dec 09, 2009 11:50 am

Re: Implementing a FSM in VHDL

Postby Case23 » Thu May 26, 2011 9:43 am

tricky wrote:The best solution to al of this is not to use a 2 process state machine. If you define the state machine in a single clocked process, all of your outputs will be registers anyway, eliminating any possible latches.


That depends on your situation, as in a one process state machine the current output depends on the last state, not on the current. So every type of state machine has its disadvantage.

one process:
process 1 (clocked): state = f(state); output = f(state)
disadvantage: output depends on last state, or in other words it is delayed by one clock cycle

two process:
process 1 (clocked): state = next_state
process 2 (combinatorial): next_state = f(state); output = f(state)
disadvantage: outputs have a combinatorial delay (bad for external pins)

three process:
process 1 (clocked): state = next_state
process 2 (combinatorial): next_state = f(state)
process 3 (clocked): output = f(next_state)
disadvantage: longer critical path

and latches are always bad 8)
Case23
 
Posts: 87
Joined: Wed May 19, 2004 9:41 am

Re: Implementing a FSM in VHDL

Postby tricky » Thu May 26, 2011 9:40 pm

That depends on your situation, as in a one process state machine the current output depends on the last state, not on the current. So every type of state machine has its disadvantage.


Thats depends on if you build a mealy or moore machine. You use the state transitions to change the outputs and the outputs depend on current state. a one process state machine solves a lot of the basic errors many people can make with 2 process state machines that lead to latches.
tricky
 
Posts: 58
Joined: Wed Dec 09, 2009 11:50 am


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