switch not being read + led not lighting

The favorite HDL language in Europe and in Universities

switch not being read + led not lighting

Postby sentry » Sun Oct 10, 2010 9:37 pm

Hi.

I have the following vhdl code on a Xilinx Spartan-3AN starter kit (apologies for the .'s but whitespace indentation seems be filtered out of my post):

process(clk)
....begin
....if rising_edge(clk) then
........test_led <= '1';
........if reset = '1' then --reset is controlled with sliding switch
............led_1 <= '1';
............led_2 <= '0';
............-- do stuff
........else
............led_1 <= '0';
............led_2 <= '1';
............-- do other stuff
........end if;
....else
....end if;
end process;

When I download it to the FPGA the test_led lights up (which I assume means that I have a periodic clock with a rising edge) but led_1 and led_2 never light up. Since reset is connected to a sliding switch that is either in the '0' or '1' state one of led_1 or led_2 should light up, correct? I've double checked my constraints file to ensure all my led's are specified and that the sliding switch that controls the 'reset' is also specified (all using appropriately modified example code from Xilinx documentation) and in another project I can successfully control a led with a sliding switch so I can't figure out why this behaves the way it does. Can anyone point out a flaw/behaviour I've missed?
sentry
 
Posts: 6
Joined: Sun Oct 10, 2010 9:05 pm
Location: South Africa

update

Postby sentry » Sun Oct 10, 2010 11:04 pm

Here is an update to my problem described above; I changed the code to (i.e. removed the clk influence):

process(reset)
....begin
....test_led <= '1';
....if reset = '1' then --reset is controlled with sliding switch
.......test_led <= '1';
.......led_1 <= '1';
.......led_2 <= '0';
........-- do stuff
....else
........test_led <= '0';
........led_1 <= '0';
........led_2 <= '1';
........-- do other stuff
....end if;
end process;

If I set reset to '1' test_led and led_1 light up and if I set reset to '0' then only led_2 lights up. Does that mean my clk signal earlier wasn't periodic? I had the following constraint in my associated UCF file:

NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50% INPUT_JITTER 20 ps;

Does that give me a 50MHz clock signal?
sentry
 
Posts: 6
Joined: Sun Oct 10, 2010 9:05 pm
Location: South Africa

Postby Case23 » Mon Oct 11, 2010 6:44 am

hi sentry

if you want spaces in your post use the code tag
Code: Select all
foo
       bar


the clock constraint in an ucf just specifies how fast your clock is (needed by synthesis). It does not generate it. Have you connected it to a clock source?
Case23
 
Posts: 87
Joined: Wed May 19, 2004 9:41 am

Postby sentry » Mon Oct 11, 2010 7:06 am

Aha! Thanks for the info, will go about figuring out how to connect the clock source. However, if you're feeling generous and want to provide a few hints I won't complain. Thanks for the help though.
sentry
 
Posts: 6
Joined: Sun Oct 10, 2010 9:05 pm
Location: South Africa

Postby Case23 » Mon Oct 11, 2010 10:46 am

hi sentry,

page 34 in the user guide (http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf i hope this is the correct one) says pin E12
Case23
 
Posts: 87
Joined: Wed May 19, 2004 9:41 am


Return to VHDL

Who is online

Users browsing this forum: No registered users and 3 guests

cron