Can you explain those VHDL codes to me?

The favorite HDL language in Europe and in Universities

Can you explain those VHDL codes to me?

Postby usbank » Sat Oct 02, 2010 12:22 pm

What value will vector e obtain after the following code:

entity t99 is

Port (

e : out STD_LOGIC_VECTOR (4 downto 0));

end t99;

architecture Behavioral of t99 is

signal a,b,c : std_logic_vector(4 downto 0);

signal d : std_logic_vector(0 to 1);

begin

a <= (1=>'0', 3=>'1', others => b(2));

b <= (1=>'1', 3=>'0', others =>c(0));

c <= (1=>'1', 3=>'0', others =>d(1));

d <= "01";

e <= a;

end Behavioral;

So whats the answer? and explain the solution to me in details, as i am a newcomer.
many thanks.
usbank
 
Posts: 3
Joined: Sat Oct 02, 2010 12:17 pm

Postby jducluzeau » Sun Oct 03, 2010 9:08 pm

Hi,

I explain you c value.
You will be able to do the rest.

signal d : std_logic_vector(0 to 1);
d <= "01";
thas means d(1)=1

c <= (1=>'1', 3=>'0', others =>d(1)); means c(1)=1,c(3)=0 and the others bits equals 1

signal a,b,c : std_logic_vector(4 downto 0);
then c='10111'

Regards
jducluzeau
 
Posts: 2
Joined: Sun Oct 03, 2010 8:16 pm
Location: france

Postby usbank » Sun Oct 03, 2010 10:47 pm

Thanks for your answer.
usbank
 
Posts: 3
Joined: Sat Oct 02, 2010 12:17 pm


Return to VHDL

Who is online

Users browsing this forum: No registered users and 3 guests

cron