Initialisation problem with 8 bit counter …

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Initialisation problem with 8 bit counter …

Postby michaels » Sat Sep 04, 2010 4:03 pm

Hi

I come from « normal » programming world and I am very pertubated by INITIALISATION procedures in VHDL code.

I have difficulty with of course the most basics : 8 bit counter…

But if we generalise, the problem goes like this ….

[this is the « correct » VHDL code. Well « correct » according to your norms which still puzzle me …]



architecture
signal var1 : std_logic_vector ( n-1 )
signal var2 : std_logic_vector ( n-1 )
signal var3 : std_logic_vector ( n-1 )

process (clock, reset)

if reset = 0 then
var1 = 0
var2 = 0
var3 = 0
else if rising edge (clock) and clock event then



end process

exit1_Q = var1
exit2_Q = var2
exit3_Q = var3
end architecture



[this is what we would be tempted to do in « normal » programming world ». We would initialise in the declaration section. Don’t you think ? So the code would go like this …]



architecture
signal var1 : std_logic_vector ( n-1 ) = 0
signal var2 : std_logic_vector ( n-1 ) = 0
signal var3 : std_logic_vector ( n-1 ) = 0

process (clock, reset)

if reset = 0 then
var1 = 0
var2 = 0
var3 = 0
else if rising edge (clock) and clock event then



end process

exit1_Q = var1
exit2_Q = var2
exit3_Q = var3
end architecture



I would like to have the point of view of a PROFICIENT VHDL programmer to give me his view. I’ve never seen this thing :

architecture
signal var1 : std_logic_vector ( n-1 ) = 0

so I guess it is wrong. Wrong or inutile/useless ?
I don’t have a simulator at home (…). Could SO simulate the code and let me know what happens ?




architecture
signal count : std_logic_vector ( n-1 ) = 0
process (clock, reset)
if reset = 0 then
count = 0
else if rising edge (clock) and clock event then
count = count + 1
end process
exit_Q = count
end architecture



what does the simulator tell ? Does it accept Initialisation at the Signal Declaration level ? ? ? ? It is true that the body of the architecture is concurrent world. So I can imagine the initialisation should not be in the Declaration Section and just stay in the reset section (I don’t have any problem with initialisation after the reset. All the components are initialised after RESET). This gives a static and « FLAT » vision of the code.

If I initiliase with zeros , am I committing a breach ? Is it Erroneous VHDL code ? That’s why I would like the opinion of a PROFICIENT VHDL. I feel very uncomfortable with this issue so I hope someone will take the time to reply to me .
michaels
 
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Joined: Sat Sep 04, 2010 3:55 pm

Postby Case23 » Mon Sep 06, 2010 8:17 am

hi michaels,

Code: Select all
signal var1 : std_logic_vector ( n-1 ) = 0


You have two errors here. First the syntax, it is easier :) . = is always comparing operator in vhdl := or <= is assignment. In this case := is the correct assigment.
Your second error is that std_logic_vector is not an integer (although you can do math on it). std_logic_vector is an array ob std_logic, which basicly is a signal wire. You not only need to specify how many wires you want (as vou did with (n-1)), but you need to define a range. This can be ether (a to b) or (c downto d). b and c are the larger numbers. a and c are the msb if you do math on it. so (n-1 downto 0) would be a could start.
And as it isnt an integer you cannot just assign a 0 to it, but you can assign an array of '0' (syntax for 0 on a std_logic) which is "00000000" (including the ").

Greetings Case
Case23
 
Posts: 87
Joined: Wed May 19, 2004 9:41 am

reply for case23

Postby michaels » Mon Sep 06, 2010 6:17 pm

thanks for the reply case23.

actually I am aware of the 2 syntax errors you pointed out. I just wanted to simplify a bit.

My point is not on syntax. I don't have any problem there (but with your intervention I'll be very careful from now on when i post some VHDL code. I'll make sure it is correct.

This is my point:

when I write/initiliase like this:

signal var1: std_logic_vector="000000"


I just want to know if both simulator and synthetiser will take them correctly.


you see . in all the VHDL code for counter, they only write


signal var1: std_logic_vector


and NEVER


signal var1: std_logic_vector="000000"



I would like to know how you do it PERSONNALLY. Do you initialise or not
(normally the inititialisation takes place after the reset and this is sufficient)


I had a look at some camecorder code. and indeed. They NEVER INITIALISE in the declaration section of the signal and only in the RESET.

I just want to know how you personnally proceed ....

(people don't initiliase in the SIGNAL declaration section. how do you proceed ??)
michaels
 
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Joined: Sat Sep 04, 2010 3:55 pm

Postby Case23 » Tue Sep 07, 2010 8:00 am

hi michaels,

initialisation is considered bad coding style by most professional people. The reason is that you cannot synthesize it to asic. synthesis to fpga and simulation works fine.
Case23
 
Posts: 87
Joined: Wed May 19, 2004 9:41 am

another reply to Mr Case23

Postby michaels » Tue Sep 07, 2010 8:13 pm

thanks Mr Case23.

Your reply is very short. But I start to understand what you mean ...


I have a vocabulary problem (don't have the word asic in my dictionary. must be specific to vhdl)

[The reason is that you cannot synthesize it to asic.]

What does it mean????? synthesize to asic.

This is how I understand it (and correct me if I'm wrong): when you initialise, it makes no sense to the synthetiser (it won't be turned into a circuit of FFs, gates, wires etc ...). That's why it is "bad coding" because it corresponds to no physical reality. So is it what you mean? I hope you can take some minutes to explain "you cannot synthetise it to asic". You'll save my life doing so.


What is your personnal approach. If i'm your student and I hand you over a code with initialisation what do you say to me? " Mike you stop it immediately. Nobody put those initialisations. You remove them immediately. I don't want to see".

I need a bossy voice to say these things to me so I'm convinced totally in the end.

what does your personnal code look like? I guess there is not a single initialisation ...
michaels
 
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Joined: Sat Sep 04, 2010 3:55 pm

Postby Case23 » Wed Sep 08, 2010 8:09 am

hi michaels,

asic means "application specific integrated circuit". which means an ic produced exactly to the specs you give. you can read wikipedia for more http://en.wikipedia.org/wiki/Application-specific_integrated_circuit. At work i have to say stop it, because we make designs for asic production. At the university it was acceptable because everybody was using fpgas.

when you initialise it make the sense to set it to a given value at the very beginning. The problem in asic is that there you use "normal" FFs which are always have undefined state in the very beginning. fpgas use a special FF with two reset signals, one can be used by your design, the other is used to set it right after loading the design into the fpga to set it to the initialisation value.
Case23
 
Posts: 87
Joined: Wed May 19, 2004 9:41 am

more trying to understand it

Postby michaels » Wed Sep 08, 2010 8:38 pm

2 remarks/questions:

1. the first reset in the fpga FF: I guess I design the reset in the Process/reset section of the code. So Ok I know how to do it.
2. The second reset in the fpga. By the way is it the reset used by what other people call the POR function or the optional GSR function. What you call: the other is used to set it right after loading the design into the fpga to set it to the initialisation value. I suppose this is the POR function you are describing. So I come to the point. How do you programm the POR: will it be the initialisation values in the definition section – which puzzle me so much – after all, this piece of information must be used somewhere. Or is there a window panel in the XST or Quartus or Synplify software that tells you: click the option: I want a POR function to be added and I define the init values of the signal in those entry boxes. Well I would like to know how you “set up” this second reset button. Configuration panel or simply the init values in the definition area?

You are familiar with university material and I’m a beginner. Do you have links for (well it will be very basic): a photo of a kit? What does a fitter look like. I’ve never seen one and heard of it so much ….(sigh). One thing I would like to know is: after burning a fpga chip, can you erase it and burn it again? What is the price of a raw fpga chip (I can’t find that in my city electronics store). Where can I order that? I just saw the zylinx website: spartan kit and cost 500$. Damn that’s expensive. They don’t say how many blank fpga chips they provide. I need to get started somewhere. And I would like to work on Asic some day. Where can I order these things and get reasonable prices?
michaels
 
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Joined: Sat Sep 04, 2010 3:55 pm

Postby Case23 » Thu Sep 09, 2010 9:51 am

hi michaels,

1.
simply the init values in the definition area


2. there seem to be some misunderstandings.
If you want some photos and better prices i recommend digilent inc. http://www.digilentinc.com/. they have nice boards for beginners. you should choose what kind of interfaces and memorys you need for what you want to do. and then choose a board and maybe some extension boards (called Pmod)

"burning" fpgas: fpgas (normal ones, there is always an exception) use an sram or a flash memory to hold a binary of your design. the sram is erased when you power off the board, the flash is erased when you give the command to erase it. when the memory is cleared you can reprogram the fpga. you can order single fpga chips, but you dont need them (only if you want to build your own board)

a fitter is just a piece of software.
Case23
 
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Joined: Wed May 19, 2004 9:41 am

reply to Mr case23

Postby michaels » Sat Sep 11, 2010 7:18 pm

I don't understand your "quote" much. (there's no comment added). I suppose it is the way to parametize the second reset (which sets right values at the very beginning). Just confirm on that. Because I got a little confused with this "quote" out of context.

Now I would like to know. How spread is this method of initialisation ??? (it is no mentioned in no book really. Besides I asked fpga progammers, in another forum, about this method of initialisation. And in fact no one will be using it. One person will be using it for simulation purposes and then remove remove it [apparently] when it comes to actual synthesis. The majority will be categorical about using FIRST. the explicit reset defined in the process body (it seems to be the only really robust way of resetting and which is 100 % portable), SECONDLY they will resort to the POR (which is a default feature. And it was mentioned by proficient people that this feature is not 100 % reliable). And then thirdly, they will resort to the "initialiser" (init values in the definition area).

You have mentioned inittialisation was "commonly spread" at uni. What is the percentage of this tendancy?

In which context did people use this form of initialisation? (to me, the FIRSTLY method is robust and portable. How come would people initialise in definition area. What is the addictional plus for doing this? (besides reading different codes camcorder etc I must admit I've never seen any use for the initialiser. But I would like to know more. after all.

In which situations did you use initialisation (in definition area) yourself? At work, you have to tell people stop it. I guess this habit has come from somewhere.
michaels
 
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Joined: Sat Sep 04, 2010 3:55 pm

Postby Case23 » Mon Sep 13, 2010 8:08 am

hi michaels,

yes, when you initiliase a signal, the fpga will use the other reset.

if you write code that may be used in an asic later, you cannot use initialisation. At work we make designs for asic, so we cannot use initialisation. At university it doen't matter because these designs will never make it to an asic.
Case23
 
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Joined: Wed May 19, 2004 9:41 am


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