i don't know how to run this code & why i didn't outoutp

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i don't know how to run this code & why i didn't outoutp

Postby cutesooos_t » Wed May 21, 2008 11:08 am

[list=][/list][/b]library ieee;
use ieee.std_logic_1164.all;

entity radial_basis is
generic (
word_length_in : integer := 18;
word_length_out : integer := 46;
values_no : integer := 6;
weights_no : integer := 6;
address_wi : integer := 16);


port (
data_in : in std_logic_vector( 0 to (word_length_in-1));
values : in std_logic_vector( 0 to(word_length_in*values_no-1));
data_out : out std_logic_vector( 0 to (word_length_out));
address : in std_logic_vector(0 to (address_wi-1));
x_r : in std_logic;
last_v_i : in std_logic;
clk, reset : in std_logic);

end radial_basis;


architecture radial_b_rtl of radial_basis is
component calc_u3
generic (

word_length_in : integer;
word_length_out : integer;
values_no : integer;
weights_no: integer);

port (
values : in std_logic_vector(0 to (word_length_in*values_no-1));
weights : in std_logic_vector( 0 to (word_length_in*weights_no-1));
data_out : out std_logic_vector( 0 to (word_length_out));
last_v_i : in std_logic;
clk, reset : in std_logic);
end component;

component BUFFERS
generic (
address_wi : integer;
values_no : integer);
port (
data_in : in std_logic_vector( 0 to 17 );
data_out : out std_logic_vector( 0 to (18*values_no-1));
address : in std_logic_vector( 0 to (address_wi-1));
wr : in std_logic;
clk, reset : in std_logic);

end component;

signal weight_w : std_logic_vector( 0 to (word_length_in*weights_no-1));

begin

NODES: calc_u3 generic map(word_length_in,word_length_out,values_no,weights_no) port map(values,weight_w,data_out,last_v_i,clk,reset);

WEIGHTS: BUFFERS generic map(address_wi,weights_no)port map(data_in,weight_w,address,x_r,clk,reset);


end radial_b_rtl;
cutesooos_t
 
Posts: 2
Joined: Wed May 21, 2008 10:46 am

i don't know how to run this code & why i don't get outp

Postby cutesooos_t » Wed May 21, 2008 11:09 am

cutesooos_t wrote:[list=][/list][/b
library ieee;
use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;


entity ADDER is

generic (wordsize : integer := 18);


port (


A, B : in std_logic_vector( 0 to (wordsize-1));



sum : out std_logic_vector( 0 to (wordsize-1));
v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);


end ADDER;




architecture ADDER_rtl of ADDER is


begin


process (clk, reset)


begin


if reset = '0' then


sum <= (others => '0');
v_o <= '0';

elsif clk'event and clk = '1' then


sum <= A + B;
v_o <= v_i;

end if;

end process;
end adder_rtl;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;


entity MULT1 is
generic ( wordsize_in:integer:=18 ;

wordsize_out : integer := 36 );


port (


A, B : in std_logic_vector(0 to (wordsize_in-1));

product : out std_logic_vector(0 to (wordsize_out-1));

v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);


end MULT1;

architecture MULT1_rtl of MULT1 is


signal prod : std_logic_vector(0 to (wordsize_in*2-1));



begin



process (clk, reset)


begin


if reset = '0' then


product <= (others => '0');
v_o <= '0';



elsif clk'event and clk = '1' then

product <= (others => prod(prod'length-1));

product(0 to (wordsize_in*2-1)) <= prod;

v_o <= v_i;

end if;

end process;

prod <= A * B;

end MULT1_rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

entity MULT2 is
generic (wordsize_in:integer := 16;
wordsize_out:integer := 40);
port (
A_1, B_1, A_2, B_2 : in std_logic_vector(0 to (wordsize_in-1));

Product_1, Product_2 : out std_logic_vector(0 to (wordsize_out-1));

v_i1, v_i2 : in std_logic ;
v_o1, v_o2 : out std_logic ;
clk , reset : in std_logic);

end MULT2;


architecture MULT2_rtl of MULT2 is

signal a, b : std_logic_vector(0 to (wordsize_in-1));

signal prod, prod_b : std_logic_vector(0 to (wordsize_in*2-1));


begin


a <= A_1 when clk = '1' else A_2;
b <= B_1 when clk = '1' else B_2;
prod <= signed(a) * signed(b);

process (clk, reset)

begin

if reset = '0' then
prod_b <= (others => '0');

elsif clk'event and clk = '0' then
prod_b <= prod;

end if;

end process;

process(clk , reset)

begin

if reset = '0' then

Product_1 <= (others => '0');
Product_2 <= (others => '0');
v_o1 <= '0';
v_o2 <= '0';

elsif clk'event and clk = '1' then

Product_1 <= (others => prod_b(prod_b'length-1));
Product_1(0 to (prod_b'length-1) ) <= prod_b;
Product_2 <= (others => prod(prod'length-1));
Product_2(0 to (prod'length-1)) <= prod;
v_o1 <= v_i1;
v_o2 <= v_i2;

end if;

end process;

end MULT2_rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity MUL3 is
generic (wordsize_in: integer := 18;
wordsize_out : integer := 46 );

port (
A, B : in std_logic_vector(0 to wordsize_in-1);

product : out std_logic_vector(0 to wordsize_out-1);

v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);

end MUL3;

architecture MULT3_rtl of MUL3 is

component MULTiplier
port(
A : in std_logic_vector (0 to 17);
B : in std_logic_vector (0 to 17);
c : in std_logic;
E : in std_logic;
R : in std_logic;
P : out std_logic_vector (0 to 35));
end component;

signal o, nr : std_logic;
signal prod : std_logic_vector(0 to (wordsize_in*2-1));

begin

o <= '1';
nr <= not reset;
product(0 to (product'length-1)) <= (others => prod(35));
product(0 to 35) <= prod;

MULT: MULTiplier port map(A,B,clk,o,nr,prod);

process (clk, reset)

begin
if reset = '0' then
v_o <= '0';
elsif clk'event and clk = '1' then
v_o <= v_i;

end if;
end process;
end MULT3_rtl;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;

entity ACCUM1 is
generic (word_length : integer := 46);
port (
data_in : in std_logic_vector( 0 to(word_length-1));
data_out : out std_logic_vector( 0 to(word_length-1));
overflow : out std_logic;
v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);
end ACCUM1;

architecture ACCUM1_rtl of ACCUM1 is
signal acc_1, acc_2 : std_logic_vector(0 to (word_length/2));
signal reg_1, reg_2 : std_logic_vector( 0 to (word_length/2-1));
signal last_value_buffer : std_logic_vector(0 to 2);
signal overflow_trig : std_logic_vector(0 to 2);
begin

process (clk, reset)

begin
if reset = '0' then
reg_1 <= (others => '0');
reg_2 <= (others => '0');
acc_1 <= (others => '0');
acc_2 <= (others => '0');
overflow_trig <= (others => '0');
overflow <= '0';
data_out <= (others => '0');
last_value_buffer <= (others => '0');

elsif clk'event and clk = '1' then
last_value_buffer <= last_value_buffer( 0 to (last_value_buffer'length-2)) & v_i;
overflow_trig <= (overflow_trig(2) or ((overflow_trig(1) xor
acc_2(acc_2'length-1)) and overflow_trig(0))) & acc_2(acc_2'length-1) &
(acc_2(acc_2'length-1) xnor reg_2(reg_2'length-1));
reg_1 <= acc_1( 0 to (reg_1'length-1));
reg_2 <= data_in( (reg_1'length) to (data_in'length-1));

if last_value_buffer(0) = '0' then
acc_1 <= ('0' & acc_1( 0 to (acc_1'length-2))) + ('0' & data_in( 0 to (word_length/2-1)));
else
acc_1 <= '0' & data_in( 0 to (word_length/2-1));
end if;

if last_value_buffer(1) = '0' then
acc_2 <= (acc_2( 1 to (acc_2'length-1)) & '1') + (reg_2 & acc_1(acc_1'length-1));
else
acc_2 <= reg_2 & '1';
data_out <= acc_2( 1 to (acc_2'length-1)) & reg_1;
overflow <= overflow_trig(overflow_trig'length-1);
overflow_trig <= (others => '0');

end if;

end if;

end process ;

v_o <= last_value_buffer(last_value_buffer'length-1);

end ACCUM1_RTL;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity ACCUM2 is

generic (word_length : integer := 46 );

port (
data_in : in std_logic_vector( 0 to (word_length-1));

data_out : out std_logic_vector(0 to (word_length-1));

overflow : out std_logic;
v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);

end ACCUM2;

architecture ACCUM2_rtl of ACCUM2 is

signal acc_reg, reg : std_logic_vector(0 to (word_length-1));
signal last_value,overflow_buffer : std_logic;

begin
process(clk, reset)

begin

if reset = '0' then

acc_reg <= (others => '0');
data_out <= (others => '0');

overflow <= '0';
overflow_buffer <= '0';

last_value <= '0';
v_o <= '0';

elsif clk'event and clk = '1' then

last_value <= v_i;
v_o <= last_value;

if (data_in(data_in'length-1) = acc_reg(acc_reg'length-1)) and (acc_reg(acc_reg'length-1) /= reg(reg'length-1)) then
overflow_buffer <= '1';
end if;

if last_value = '0' then

acc_reg <= reg;
else
acc_reg <= data_in;
data_out <= acc_reg;
overflow <= overflow_buffer;
overflow_buffer <= '0';
end if;

end if;

end process;

reg <= acc_reg + data_in;

end ACCUM2_rtl;

library ieee;
use ieee.std_logic_1164.all;

entity calc_u1 is

generic (word_length_in : integer := 18;
word_length_out : integer := 46);
port (
value : in std_logic_vector(0 to (word_length_in-1));

weight : in std_logic_vector(0 to (word_length_in-1));

acc_out : out std_logic_vector(0 to (word_length_out-1));

overflow : out std_logic;

v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);
end calc_u1;

architecture calc_u1_rtl of calc_u1 is

component ADDER
generic (wordsize:integer);
port (


A, B : in std_logic_vector( 0 to (wordsize-1));

sum : out std_logic_vector( 0 to (wordsize-1));
v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);

end component;

component MULT1
generic (wordsize_in : integer;
wordsize_out : integer);
port (
A, B : in std_logic_vector(0 to (wordsize_in-1));

product : out std_logic_vector(0 to (wordsize_out-1));
v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);

end component;

component ACCUM1
generic (word_length : integer);
port (
data_in : in std_logic_vector( 0 to(word_length-1));
data_out : out std_logic_vector( 0 to(word_length-1));
overflow : out std_logic;
v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);

end component;

signal sumw : std_logic_vector(0 to (word_length_in-1));
signal productw : std_logic_vector(0 to (word_length_out-1));
signal last_value_w_1, last_value_w_2 : std_logic;

begin

ADD: ADDER generic map(word_length_in) port map(value,weight,sumw,v_i,last_value_w_1,clk,reset);

MULT: MULT1 generic map(word_length_in,word_length_out) port map(sumw,sumw,productw,last_value_w_1,last_value_w_1,clk,reset);

ACC: ACCUM1 generic map(word_length_out) port map(productw,acc_out,overflow,last_value_w_2,v_o,clk,reset);

end calc_u1_rtl;

library ieee;
use ieee.std_logic_1164.all;


entity calc_u2 is
generic (
word_length_in : integer := 18;
word_length_out : integer := 42);


port (
v_1, v_2 : in std_logic_vector(0 to (word_length_in-1));
w_1, w_2 : in std_logic_vector(0 to (word_length_in-1));

acc_out_1, acc_out_2 : out std_logic_vector(0 to (word_length_out-1));

overflow_1, overflow_2 : out std_logic;

v_i1, v_i2 : in std_logic ;
v_o1, v_o2 : out std_logic ;

clk, reset : in std_logic);
end calc_u2;


architecture calc_u2_rtl of calc_u2 is

component ADDER
generic (wordsize:integer);
port (
A, B : in std_logic_vector( 0 to (wordsize-1));

sum : out std_logic_vector( 0 to (wordsize-1));
v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);
end component;

component MULT2
generic (wordsize_in:integer;
wordsize_out:integer);
port (
A_1, B_1, A_2, B_2 : in std_logic_vector(0 to (wordsize_in-1));

Product_1, Product_2 : out std_logic_vector(0 to (wordsize_out-1));

v_i1, v_i2 : in std_logic ;
v_o1, v_o2 : out std_logic ;
clk , reset : in std_logic);
end component;

component ACCUM1
generic (word_length : integer);

port (
data_in : in std_logic_vector( 0 to(word_length-1));
data_out : out std_logic_vector( 0 to(word_length-1));
overflow : out std_logic;
v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);
end component;

signal sumw_1, sumw_2 : std_logic_vector(0 to (word_length_in-1));
signal prodw_1, prodw_2 : std_logic_vector(0 to (word_length_out-1));
signal last_value_wire_1_1, last_value_wire_2_1, last_value_wire_1_2,last_value_wire_2_2 : std_logic;

begin

add_1: ADDER generic map(word_length_in) port map (v_1,w_1,sumw_1,v_i1,last_value_wire_1_1,clk,reset);

ADD_2: ADDER generic map(word_length_in) port map (v_2,w_2,sumw_2,v_i2,last_value_wire_1_2,clk,reset);

MULT: MULT2 generic map(word_length_in,word_length_out) port map (sumw_1,sumw_1,sumw_2,sumw_2,prodw_1,prodw_2,last_value_wire_1_1, last_value_wire_2_1, last_value_wire_1_2,last_value_wire_2_2,clk,reset);

ACC_1: ACCUM1 generic map(word_length_out) port map (prodw_1,acc_out_1,overflow_1,last_value_wire_2_1,v_o1,clk,reset);

ACC_2: ACCUM1 generic map(word_length_out) port map (prodw_2,acc_out_2,overflow_2,last_value_wire_2_2,v_o2,clk,reset);

end calc_u2_rtl;

library ieee;
use ieee.std_logic_1164.all;

entity node_1 is
generic (word_length_in : integer := 16;
word_length_out : integer := 42);
port (
value : in std_logic_vector(0 to (word_length_in-1));

weight : in std_logic_vector(0 to (word_length_out-1));

acc_out : out std_logic_vector(0 to (word_length_in-1));

overflow : out std_logic;
v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);
end node_1;

architecture node_1_rtl of node_1 is

component MULT1
generic ( wordsize_in:integer ;

wordsize_out : integer );


port (

A, B : in std_logic_vector(0 to (wordsize_in-1));

product : out std_logic_vector(0 to (wordsize_out-1));

v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);
end component;


component ACCUM1
generic (word_length : integer);

port (
data_in : in std_logic_vector( 0 to(word_length-1));
data_out : out std_logic_vector( 0 to(word_length-1));
overflow : out std_logic;
v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);
end component;

signal prodw : std_logic_vector(0 to (word_length_out-1));
signal last_value_wire_1 : std_logic;

begin

MULT: MULT1 generic map(word_length_in,word_length_out) port map (value,weight,prodw,v_i,last_value_wire_1,clk,reset);
ACC: ACCUM1 generic map(word_length_out) port map (prodw,acc_out,overflow,last_value_wire_1,v_o,clk,reset);


end node_1_rtl ;

library ieee;
use ieee.std_logic_1164.all;

entity node_2 is
generic (word_length_in : integer := 18;
word_length_out : integer := 42);

port (

v_1, v_2 : in std_logic_vector(0 to (word_length_in-1));
w_1, w_2 : in std_logic_vector(0 to (word_length_in-1));
acc_out_1, acc_out_2 : out std_logic_vector(0 to (word_length_out-1));
overflow_1, overflow_2 : out std_logic;

v_i1, v_i2 : in std_logic ;
v_o1, v_o2 : out std_logic ;

clk, reset : in std_logic);
end node_2;

architecture node2_rtl of node_2 is

component MULT2
generic (wordsize_in:integer;
wordsize_out:integer);
port (
A_1, B_1, A_2, B_2 : in std_logic_vector(0 to (wordsize_in-1));

Product_1, Product_2 : out std_logic_vector(0 to (wordsize_out-1));

v_i1, v_i2 : in std_logic ;
v_o1, v_o2 : out std_logic ;

clk, reset : in std_logic);
end component;


component ACCUM1
generic (word_length : integer);

port (
data_in : in std_logic_vector( 0 to(word_length-1));
data_out : out std_logic_vector( 0 to(word_length-1));
overflow : out std_logic;
v_i : in std_logic;
v_o: out std_logic;
clk, reset : in std_logic);
end component;

signal prodw_1, prodw_2 : std_logic_vector(0 to (word_length_out-1));
signal last_value_wire_1_1, last_value_wire_1_2 : std_logic;

begin

MULT: MULT2 generic map(word_length_in,word_length_out) port map(v_1,w_1,v_2,w_2,prodw_1,prodw_2,v_i1,v_i2,last_value_wire_1_1,last_value_wire_1_2,clk,reset);

ACC_1: ACCUM1 generic map(word_length_out) port map(prodw_1,acc_out_1,overflow_1,last_value_wire_1_1,v_o1,clk,reset);
ACC_2: ACCUM1 generic map(word_length_out) port map(prodw_2,acc_out_2,overflow_2,last_value_wire_1_2,v_o2,clk,reset);


end node2_rtl ;


library ieee;
use ieee.std_logic_1164.all;

entity grid_1 is

generic (

word_length_in : integer := 8;
word_length_out : integer := 20;
values_no : integer := 4;
weights_no : integer := 4);

port (
values : in std_logic_vector(0 to (word_length_in*values_no-1));

weights : in std_logic_vector(0 to (word_length_in*weights_no-1));


data_out : out std_logic_vector(0 to((word_length_out+1)*values_no*weights_no-1));

v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);

end grid_1;

architecture grid_1_rtl of grid_1 is

component calc_u1

generic (
word_length_in : integer;
word_length_out : integer);
port (
value : in std_logic_vector(0 to (word_length_in-1));

weight : in std_logic_vector(0 to (word_length_in-1));

acc_out : out std_logic_vector(0 to (word_length_in-1));

overflow : out std_logic;

v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);
end component;

type value_b is array ( 0 to (values_no-1)) of std_logic_vector(0 to (word_length_in-1));

type weight_b is array (0 to (weights_no-1)) of std_logic_vector(0 to (word_length_in-1));

type acc is array (0 to (weights_no-1)) of std_logic_vector(0 to (word_length_out-1));

type acc_b is array ( 0 to (values_no-1)) of acc;

type oVerflow_b is array ( 0 to (values_no-1)) of std_logic_vector(0 to (weights_no-1));

signal value_w: value_b;
signal weight_w: weight_b;
signal acc_w : acc_b;
signal overflow_w : overflow_b;
signal last_value_wires : overflow_b;


begin

VALUES_IN: for i in 0 to (values_no-1) generate

value_w(i) <= values( (word_length_in*i) to (word_length_in*(i+1)-1));

end generate VALUES_IN;


WEIGHTS_IN: for i in 0 to (weights_no-1) generate

weight_w(i) <= weights( (word_length_in*i) to (word_length_in*(i+1)-1));

end generate WEIGHTS_IN;

ACC_OUT_VALUE: for i in 0 to (values_no-1) generate

ACC_OUT_WEIGHT: for j in 0 to (values_no-1) generate

data_out(((word_length_out+1)*(weights_no*i+j)) to ((word_length_out+1)*(weights_no*i+j+1)-1)) <= overflow_w(i)(j) &acc_w(i)(j);

end generate ACC_OUT_WEIGHT;
end generate ACC_OUT_VALUE;

VALUE: for i in 0 to (values_no-1) generate

WEIGHT: for j in 0 to (values_no-1) generate

UNIT: calc_u1 generic map(word_length_in,word_length_out) port map(value_w(i),weight_w(j),acc_w(i)(j),overflow_w(i)(j),v_i,last_value_wires(i)(j),clk,reset);

end generate WEIGHT;
end generate VALUE;

v_o <= last_value_wires(0)(0);

end grid_1_rtl;

library ieee;
use ieee.std_logic_1164.all;

entity grid_2 is
generic (
word_length_in : integer := 8;
word_length_out : integer := 20;
values_no : integer := 4;
weights_no : integer := 4);

port (
values : in std_logic_vector(0 to (word_length_in*values_no-1));

weights : in std_logic_vector(0 to (word_length_in*weights_no-1));

data_out : out std_logic_vector(0 to ((word_length_out+1)*values_no*weights_no-1));

v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);

end grid_2;

architecture grid2_rtl of grid_2 is

component calc_u2
generic (word_length_in : integer ;
word_length_out : integer );

port (
v_1, v_2 : in std_logic_vector(0 to (word_length_in-1));
w_1, w_2 : in std_logic_vector(0 to (word_length_out-1));

acc_1, acc_2 : out std_logic_vector(0 to (word_length_out-1));

overflow_1, overflow_2 : out std_logic;

v_i1, v_i2 : in std_logic ;
v_o1, v_o2 : out std_logic ;

clk, reset : in std_logic);

end component;

type v_bus is array ( 0 to (values_no-1)) of std_logic_vector(0 to (word_length_in-1));

type w_bus is array (0 to (weights_no-1)) of std_logic_vector(0 to (word_length_in-1));

type acc is array (0 to (weights_no-1)) of std_logic_vector(0 to (word_length_out-1));

type acc_bus is array ( 0 to (values_no-1)) of acc;

type oVerflow_bus is array ( 0 to (values_no-1)) of std_logic_vector(0 to (weights_no-1));

signal value_w: v_bus;
signal weight_w: w_bus;
signal acc_w : acc_bus;
signal overflow_w : overflow_bus;
signal last_value_wires : overflow_bus;

begin

VALUES_IN: for i in 0 to (values_no-1) generate

value_w(i) <= values( (word_length_in*i) to (word_length_in*(i+1)-1));

end generate VALUES_IN;


WEIGHTS_IN: for i in 0 to (weights_no-1) generate

weight_w(i) <= weights( (word_length_in*i) to (word_length_in*(i+1)-1));

end generate WEIGHTS_IN;

ACC_OUT_VALUE: for i in 0 to (values_no-1) generate

ACC_OUT_WEIGHT: for j in 0 to (values_no-1) generate

data_out(((word_length_out+1)*(weights_no*i+j)) to ((word_length_out+1)*(weights_no*i+j+1)-1)) <= overflow_w(i)(j) &acc_w(i)(j);

end generate ACC_OUT_WEIGHT;
end generate ACC_OUT_VALUE;

VALUE: for i in 0 to (values_no-1) generate

WEIGHT: for j in 0 to (values_no-1) generate

UNIT: calc_u2 generic map(word_length_in,word_length_out)port map(value_w(i),value_w(i),weight_w(j*2),weight_w(j*2+1),
acc_w(i)(j*2),acc_w(i)(j*2+1),overflow_w(i)(j*2),overflow_w(i)(j*2+1),v_i,v_i,last_value_wires(i)(j*2),last_value_wires(i)(j*2+1),clk,reset);


end generate WEIGHT;
end generate VALUE;


end grid2_rtl;

library ieee;
use ieee.std_logic_1164.all;

entity MUX is
generic (word_length : integer := 8;
inputs_no : integer := 16);
port (
data_in : in std_logic_vector(0 to (word_length*inputs_no-1));

data_out : out std_logic_vector(0 to (word_length-1));

port_enables : in std_logic_vector(0 to (inputs_no-1) ));

end MUX;

architecture MUX_rtl of MUX is
begin


S: for i in 0 to inputs_no-1 generate

CON_1: data_out <= data_in((word_length*i) to (word_length*(i+1)-1)) when
port_enables(i)='1' else (others => 'Z');


end generate S;

library ieee;
use ieee.std_logic_1164.all;

entity r_counter is
generic (width : integer := 8);
port (
data_out : out std_logic_vector( 0 to (width-1));

clk, reset, count_enable : in std_logic);
end r_counter;

architecture r_counter_rtl of r_counter is
signal buff : std_logic_vector( 0 to (width-1));

begin

process (clk, reset)
begin
if reset = '0' then
buff <= (others => '0');
buff(width-1) <= '1';

elsif clk'event and clk = '1' then

if count_enable='1' or buff(width-1)='0' then
buff <= buff(0 to (width-2)) & buff(width-1);
end if;

end if;


end process;
data_out <= buff;
end r_counter_rtl;

library ieee;
use ieee.std_logic_1164.all;
entity calc_u3 is
generic (

word_length_in : integer := 18;
word_length_out : integer := 42;
values_no : integer := 2;
weights_no: integer := 2);

port (
values : in std_logic_vector(0 to (word_length_in*values_no-1));
weights : in std_logic_vector( 0 to (word_length_in*weights_no-1));
data_out : out std_logic_vector( 0 to (word_length_out));

last_v_i : in std_logic;

clk, reset : in std_logic);

end calc_u3;


architecture calc_u3_rtl of calc_u3 is
component grid_1
generic (

word_length_in : integer;
word_length_out : integer;
values_no : integer;
weights_no : integer);

port (
values : in std_logic_vector(0 to (word_length_in*values_no-1));

weights : in std_logic_vector(0 to (word_length_in*weights_no-1));


data_out : out std_logic_vector(0 to((word_length_out+1)*values_no*weights_no-1));

v_i : in std_logic;
v_o: out std_logic;

clk, reset : in std_logic);

end component;

component MUX
generic (word_length : integer;
inputs_no : integer );
port (
data_in : in std_logic_vector(0 to (word_length*inputs_no-1));

data_out : out std_logic_vector(0 to (word_length-1));

port_enables : in std_logic_vector(0 to (inputs_no-1) ));
end component;


component r_counter
generic (width : integer);
port (
data_out : out std_logic_vector( 0 to (width-1));

clk, reset, count_enable : in std_logic);
end component;

signal acc_w :std_logic_vector( 0 to ((word_length_out+1)*values_no*weights_no-1));
signal port_w : std_logic_vector( 0 to (values_no*weights_no-1));
signal last_value_w : std_logic;

begin
GRID: grid_1 generic map(word_length_in,word_length_out,values_no,weights_no) port map(values,weights,acc_w,last_v_i,last_value_w,clk,reset);

MUX_1: MUX generic map(word_length_out+1,values_no*weights_no) port map(acc_w,data_out,port_w);

R_CNT: r_counter generic map(values_no*weights_no) port map(port_w,clk,reset,last_value_w);

end calc_u3_rtl;


library ieee;
use ieee.std_logic_1164.all;

entity radial_basis is
generic (
word_length_in : integer := 18;
word_length_out : integer := 46;
values_no : integer := 6;
weights_no : integer := 6;
address_wi : integer := 16);


port (
data_in : in std_logic_vector( 0 to (word_length_in-1));
values : in std_logic_vector( 0 to(word_length_in*values_no-1));
data_out : out std_logic_vector( 0 to (word_length_out));
address : in std_logic_vector(0 to (address_wi-1));
x_r : in std_logic;
last_v_i : in std_logic;
clk, reset : in std_logic);

end radial_basis;


architecture radial_b_rtl of radial_basis is
component calc_u3
generic (

word_length_in : integer;
word_length_out : integer;
values_no : integer;
weights_no: integer);

port (
values : in std_logic_vector(0 to (word_length_in*values_no-1));
weights : in std_logic_vector( 0 to (word_length_in*weights_no-1));
data_out : out std_logic_vector( 0 to (word_length_out));
last_v_i : in std_logic;
clk, reset : in std_logic);
end component;

component BUFFERS
generic (
address_wi : integer;
values_no : integer);
port (
data_in : in std_logic_vector( 0 to 17 );
data_out : out std_logic_vector( 0 to (18*values_no-1));
address : in std_logic_vector( 0 to (address_wi-1));
wr : in std_logic;
clk, reset : in std_logic);

end component;

signal weight_w : std_logic_vector( 0 to (word_length_in*weights_no-1));

begin

NODES: calc_u3 generic map(word_length_in,word_length_out,values_no,weights_no) port map(values,weight_w,data_out,last_v_i,clk,reset);

WEIGHTS: BUFFERS generic map(address_wi,weights_no)port map(data_in,weight_w,address,x_r,clk,reset);


end radial_b_rtl;
cutesooos_t
 
Posts: 2
Joined: Wed May 21, 2008 10:46 am


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