Altera Quartus 6.1 Timing Analysis Question

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Altera Quartus 6.1 Timing Analysis Question

Postby epatters » Mon Apr 16, 2007 1:24 pm

I am using the Altera Quartus 6.1 Webpack and I think I might have a timing problem. Is there a way I can ask the timing analyzer to give me a time for how long it takes from set point to the last possible filtered point?

That sounds confusing, so I will try again. I have a "latch" register which I set via a isa write to my board. I then read some of the boards registers knowing that my values won't change since I "latched" them. I think I might be seeing an issue where I am reading the values before the latched signal reaches all my blocks which sets the new registers value for read.

I would like to know the longest possible time it takes for that "latch" registers values to get filtered down to all of my blocks.

It seems simple but I can't intuituviely figure it out, does anyone know how to do this in Quartus?

-Eric
epatters
 
Posts: 2
Joined: Mon Apr 16, 2007 1:10 pm
Location: MI

Postby epatters » Mon Apr 16, 2007 6:36 pm

Another question:

I am finding that I can put settings on registers to make them fast input and fast output registers. Does anyone know what exactly this doing for me?
epatters
 
Posts: 2
Joined: Mon Apr 16, 2007 1:10 pm
Location: MI


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