fpga4fun spi slave

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fpga4fun spi slave

Postby blueiceice » Wed Dec 07, 2011 2:28 pm

HI everyone
i have some question
i use http://www.fpga4fun.com/SPI2.html code
and write the test bench
but MOSI is fail
anyone know this
//`timescale 10ns/100ps
module tb_spigpio;

reg clk = 0;
reg SCK = 0;
reg SSEL;
reg MOSI;
reg [7:0] data;
wire MISO;
wire gpioout;
integer i;

spi_slave U0(clk, SCK, MOSI, MISO, SSEL, gpioout);
initial
begin
i = 0;
data = 8'b10101010;
SSEL = 1'b1;
#5 SSEL = 1'b0;
for (i = 0; i<8; i = i+1)
begin
#20 SCK = 1;
#20 SCK = 0;
end
#5 SSEL = 1'b1;
end
[/code]
blueiceice
 
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Joined: Wed Dec 07, 2011 2:03 pm

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