Xilinx makes using PCI express easy - they provide a free PCI Express core (called "Endpoint Block Plus") and a wizard to configure it, all that in their free version of ISE - ISE WebPack.
So let's fire up Xilinx CORE generator and select Endpoint Block Plus.
The core is inactive, we need to use File --> New Project to create a project and select an FPGA (here we are using a Dragon-E so we select Virtex-5)...
... and also select your favorite language (in the "Generation" tab).
Now the Endpoint Block Plus core becomes active and you can double-click on it to start the wizard.
On the first page, name your component. Here we chose "my_endpoint_blk_plus". The rest is ok for Dragon-E, so click "Next >".
Now you can change the vendor/device IDs...
... and the address spaces.
The next pages are without much interest, so click on "Generate" to generate the core and its documentation.
We are now ready to create our first PCI Express FPGA bitfile, program it in an FPGA and generate real PCI Express traffic.